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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� ATMEGA128A-ANR
寤犲晢锛� Atmel
鏂囦欢闋佹暩(sh霉)锛� 115/386闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU AVR 128K FLASH 64TQFP
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� megaAVR Introduction
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1,000
绯诲垪锛� AVR® ATmega
鏍稿績铏曠悊鍣細 AVR
鑺珨灏哄锛� 8-浣�
閫熷害锛� 16MHz
閫i€氭€э細 EBI/EMI锛孖²C锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯/寰�(f霉)浣嶏紝POR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 53
绋嬪簭瀛樺劜鍣ㄥ閲忥細 128KB锛�64K x 16锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 4K x 8
RAM 瀹归噺锛� 4K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2.7 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 105°C
灏佽/澶栨锛� 64-TQFP
鍖呰锛� 甯跺嵎 (TR)
鍏跺畠鍚嶇ū锛� ATMEGA128A-ANR-ND
ATMEGA128A-ANRTR
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201
8151H鈥揂VR鈥�02/11
ATmega128A
21. Two-wire Serial Interface
21.1
Features
Simple yet Powerful and Flexible Communication Interface, only Two Bus Lines Needed
Both Master and Slave Operation Supported
Device can Operate as Transmitter or Receiver
7-bit Address Space allows up to 128 Different Slave Addresses
Multi-master Arbitration Support
Up to 400kHz Data Transfer Speed
Slew-rate Limited Output Drivers
Noise Suppression Circuitry Rejects Spikes on Bus Lines
Fully Programmable Slave Address with General Call Support
Address Recognition Causes Wake-up when AVR is in Sleep Mode
21.2
Two-wire Serial Interface Bus Definition
The Two-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The
TWI protocol allows the systems designer to interconnect up to 128 different devices using only
two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hard-
ware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All
devices connected to the bus have individual addresses, and mechanisms for resolving bus
contention are inherent in the TWI protocol.
Figure 21-1. TWI Bus Interconnection
21.2.1
TWI Terminology
The following definitions are frequently encountered in this section.
Device 1
Device 2
Device 3
Device n
SDA
SCL
........
R1
R2
V
CC
Table 21-1.
TWI Terminology
Term
Description
Master
The device that initiates and terminates a transmission. The master also generates the
SCL clock
Slave
The device addressed by a master
Transmitter
The device placing data on the bus
Receiver
The device reading data from the bus
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
VE-B5R-IX-F4 CONVERTER MOD DC/DC 7.5V 75W
VE-B5R-IX-F2 CONVERTER MOD DC/DC 7.5V 75W
VE-B5R-IX-F1 CONVERTER MOD DC/DC 7.5V 75W
AT89C51CC01UA-RLRUM IC 8051 MCU 32K FLASH 44-VQFP
VE-B5R-IW-F4 CONVERTER MOD DC/DC 7.5V 100W
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