1. WPx, WDx, RLx, RPx, and RDx are common to all pins within the same port. clk
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鍨嬭櫉锛� ATMEGA128A-ANR
寤犲晢锛� Atmel
鏂囦欢闋佹暩(sh霉)锛� 357/386闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC MCU AVR 128K FLASH 64TQFP
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妯欐簴鍖呰锛� 1,000
绯诲垪锛� AVR® ATmega
鏍稿績铏曠悊鍣細 AVR
鑺珨灏哄锛� 8-浣�
閫熷害锛� 16MHz
閫i€氭€э細 EBI/EMI锛孖²C锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯/寰╀綅锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 53
绋嬪簭瀛樺劜鍣ㄥ閲忥細 128KB锛�64K x 16锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶у皬锛� 4K x 8
RAM 瀹归噺锛� 4K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2.7 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 105°C
灏佽/澶栨锛� 64-TQFP
鍖呰锛� 甯跺嵎 (TR)
鍏跺畠鍚嶇ū锛� ATMEGA128A-ANR-ND
ATMEGA128A-ANRTR
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72
8151H鈥揂VR鈥�02/11
ATmega128A
Note:
1. WPx, WDx, RLx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP,
and PUD are common to all ports. All other signals are unique for each pin.
Table 12-1 summarizes the function of the overriding signals. The pin and port indexes from Fig-
ure 12-6 are not shown in the succeeding tables. The overriding signals are generated internally
in the modules having the alternate function.
The following subsections shortly describes the alternate functions for each port, and relates the
overriding signals to the alternate function. Refer to the alternate function description for further
details.
Table 12-1.
Generic Description of Overriding Signals for Alternate Functions.
Signal
Name
Full Name
Description
PUOE
Pull-up
Override Enable
If this signal is set, the pull-up enable is controlled by the PUOV
signal. If this signal is cleared, the pull-up is enabled when
{DDxn, PORTxn, PUD} = 0b010.
PUOV
Pull-up
Override Value
If PUOE is set, the pull-up is enabled/disabled when PUOV is
set/cleared, regardless of the setting of the DDxn, PORTxn, and
PUD Register bits.
DDOE
Data Direction
Override Enable
If this signal is set, the Output Driver Enable is controlled by the
DDOV signal. If this signal is cleared, the Output driver is
enabled by the DDxn Register bit.
DDOV
Data Direction
Override Value
If DDOE is set, the Output Driver is enabled/disabled when
DDOV is set/cleared, regardless of the setting of the DDxn
Register bit.
PVOE
Port Value
Override Enable
If this signal is set and the Output Driver is enabled, the port
value is controlled by the PVOV signal. If PVOE is cleared, and
the Output Driver is enabled, the port Value is controlled by the
PORTxn Register bit.
PVOV
Port Value
Override Value
If PVOE is set, the port value is set to PVOV, regardless of the
setting of the PORTxn Register bit.
DIEOE
Digital Input
Enable Override
Enable
If this bit is set, the Digital Input Enable is controlled by the
DIEOV signal. If this signal is cleared, the Digital Input Enable is
determined by MCU-state (Normal mode, Sleep modes).
DIEOV
Digital Input
Enable Override
Value
If DIEOE is set, the Digital Input is enabled/disabled when
DIEOV is set/cleared, regardless of the MCU state (Normal
mode, Sleep modes).
DI
Digital Input
This is the Digital Input to alternate functions. In the figure, the
signal is connected to the output of the schmitt trigger but
before the synchronizer. Unless the Digital Input is used as a
clock source, the module with the alternate function will use its
own synchronizer.
AIO
Analog
Input/output
This is the Analog Input/output to/from alternate functions. The
signal is connected directly to the pad, and can be used bi-
directionally.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
VE-B5R-IX-F4 CONVERTER MOD DC/DC 7.5V 75W
VE-B5R-IX-F2 CONVERTER MOD DC/DC 7.5V 75W
VE-B5R-IX-F1 CONVERTER MOD DC/DC 7.5V 75W
AT89C51CC01UA-RLRUM IC 8051 MCU 32K FLASH 44-VQFP
VE-B5R-IW-F4 CONVERTER MOD DC/DC 7.5V 100W
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