參數(shù)資料
型號(hào): ATTINY13A-SSHR
廠商: Atmel
文件頁(yè)數(shù): 13/67頁(yè)
文件大?。?/td> 0K
描述: MCU AVR 1KB FLASH 20MHZ 8SOIC
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
tinyAVR Introduction
標(biāo)準(zhǔn)包裝: 1
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 20MHz
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 6
程序存儲(chǔ)器容量: 1KB(512 x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: ATTINY13A-SSHRDKR
12
8126F–AVR–05/12
ATtiny13A
4.6
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
CPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 4-4 on page 12 shows the parallel instruction fetches and instruction executions enabled
by the Harvard architecture and the fast access Register File concept. This is the basic pipelin-
ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions
per cost, functions per clocks, and functions per power-unit.
Figure 4-4.
The Parallel Instruction Fetches and Instruction Executions
Figure 4-5 on page 12 shows the internal timing concept for the Register File. In a single clock
cycle an ALU operation using two register operands is executed, and the result is stored back to
the destination register.
Figure 4-5.
Single Cycle ALU Operation
4.7
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate Program Vector in the Program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt.
The lowest addresses in the Program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 45. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1
T2
T3
T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1
T2
T3
T4
clk
CPU
相關(guān)PDF資料
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ATTINY13A-SHR MCU AVR 1KB FLASH 20MHZ 8SOIC
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