參數(shù)資料
型號(hào): ATTINY15L-1PU
廠商: Atmel
文件頁(yè)數(shù): 14/85頁(yè)
文件大小: 0K
描述: IC MCU AVR 1K FLASH 1.6MHZ 8-DIP
標(biāo)準(zhǔn)包裝: 50
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 1.6MHz
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 6
程序存儲(chǔ)器容量: 1KB(512 x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 64 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-DIP(0.300",7.62mm)
包裝: 管件
21
ATtiny15L
1187H–AVR–09/07
vector $003) is executed if a compare match A in Timer/Counter1 occurs, i.e., when the
OCF1A bit is set (one) in the Timer/Counter Interrupt Flag Register (TIFR).
Bit 5..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny15L and always read as zero.
Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector
$004) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set
(one) in the Timer/Counter Interrupt Flag Register (TIFR).
Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector
$005) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set
(one) in the Timer/Counter Interrupt Flag Register (TIFR).
Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny15L and always reads as zero.
The Timer/Counter Interrupt
Flag Register – TIFR
Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny15L and always reads as zero.
Bit 6 – OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and
the data value in OCR1A (Output Compare Register 1A). OCF1A is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, OCF1A
is cleared by writing a logical “1” to the flag. When the I-bit in SREG, OCIE1A, and
OCF1A are set (one), the Timer/Counter1 compare match A interrupt is executed.
Bits 5..3 – Res: Reserved bits
These bits are reserved bits in the ATtiny15L and always read as zero.
Bit 2 – TOV1: Timer/Counter1 Overflow Flag
The bit TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV1 is cleared by writing a logical “1” to the flag. When the SREG I-bit, TOIE1
(T im er/Co u n t er1 Ove r flow Inte rrup t En able) an d TO V1 a r e set (o ne) , th e
Timer/Counter1 Overflow Interrupt is executed.
Bit
7
6
543
21
0
$38
OCF1A
–––
TOV1
TOV0
TIFR
Read/Write
R
R/W
R
R/W
R
Initial Value
0
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