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| 型號： | ATTINY15L-1PU |
| 廠商： | Atmel |
| 文件頁數(shù)： | 3/85頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU AVR 1K FLASH 1.6MHZ 8-DIP |
| 標準包裝： | 50 |
| 系列： | AVR® ATtiny |
| 核心處理器： | AVR |
| 芯體尺寸： | 8-位 |
| 速度： | 1.6MHz |
| 外圍設備： | 欠壓檢測/復位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 6 |
| 程序存儲器容量： | 1KB（512 x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 64 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉換器： | A/D 4x10b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
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11
ATtiny15L
1187H–AVR–09/07
Note:
1. Reserved and unused locations are not shown in the table.
All ATtiny15L I/O and peripheral registers are placed in the I/O space. The I/O locations
are accessed by the IN and OUT instructions transferring data between the 32 general
purpose working registers and the I/O space. I/O Registers within the address range
$00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these regis-
ters, the value of single bits can be checked by using the SBIS and SBIC instructions.
Refer to the instruction set chapter for more details. For compatibility with future
devices, reserved bits should be written zero if accessed. Reserved I/O memory
addresses should never be written.
The I/O and Peripheral Control Registers are explained in the following sections.
The Status Register – SREG
The AVR Status Register – SREG – at I/O space location $3F is defined as:
Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in the Interrupt Mask Registers –
GIMSK and TIMSK. If the Global Interrupt Enable Register is cleared (zero), none of the
interrupts are enabled independent of the GIMSK and TIMSK values. The I-bit is cleared
by hardware after an interrupt has occurred, and is set by the RETI instruction to enable
subsequent interrupts.
Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source
and destination for the operated bit. A bit from a register in the Register File can be cop-
ied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the
Register File by the BLD instruction.
Bit 5 – H: Half-carry Flag
The Half-carry Flag H indicates a half-carry in some arithmetic operations. See the
Instruction Set description for detailed information.
Bit 4 – S: Sign Bit, S = N
⊕ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Comple-
ment Overflow Flag V. See the Instruction Set description for detailed information.
Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See
the Instruction Set description for detailed information.
$06
ADCSR
ADC Control and Status Register
$05
ADCH
ADC Data Register High
$04
ADCL
ADC Data Register Low
Table 2. ATtiny15L I/O Space
(1) (Continued)
Address Hex
Name
Function
Bit
765
432
10
$3F
I
T
H
S
V
N
Z
C
SREG
Read/Write
R/W
Initial Value
0
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ATTINY15L-1SC | 功能描述:8位微控制器 -MCU AVR 1K FLASH 64B EE ADC 3V 1.6MHZ RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| ATTINY15L-1SC SL383 | 制造商:Atmel Corporation 功能描述:MCU 8-Bit ATtiny AVR RISC 1KB Flash 3.3V/5V 8-Pin SOIC EIAJ T/R |
| ATTINY15L-1SI | 功能描述:8位微控制器 -MCU AVR 1K FLASH 64B EE ADC 3V 1.6MHZ RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| ATTINY15L-1SI SL383 | 制造商:Atmel Corporation 功能描述:MCU 8-bit ATtiny AVR RISC 1KB Flash 3.3V/5V 8-Pin SOIC EIAJ T/R |
| ATTINY15L-1SITRSL#QS309 | 制造商:Atmel Corporation 功能描述:ATLATTINY15L-1SITRSL#QS309 PGMD FOR AAPL |
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