參數(shù)資料
型號: ATTINY15L-1SI
廠商: Atmel
文件頁數(shù): 30/85頁
文件大?。?/td> 0K
描述: IC AVR MCU 1K FLASH 2.7V SO8
標(biāo)準(zhǔn)包裝: 95
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 1.6MHz
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 6
程序存儲器容量: 1KB(512 x 16)
程序存儲器類型: 閃存
EEPROM 大小: 64 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.209",5.30mm 寬)
包裝: 管件
36
ATtiny15L
1187H–AVR–09/07
EEPROM Read/Write
Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time is in the range of 4.6 - 8.2 ms, depending on the frequency of the
calibrated RC Oscillator. See Table 16 for details. A self-timing function however, lets
the user software detect when the next byte can be written. If the user code contains
code that writes the EEPROM, some precautions must be taken. In heavily filtered
power supplies, V
CC is likely to rise or fall slowly on Power-up/down. This causes the
device for some period of time to run at a voltage lower than specified as minimum for
the clock frequency used. CPU operation under these conditions is likely to cause the
Program Counter to perform unintentional jumps and eventually execute the EEPROM
write code. To secure EEPROM integrity, the user is advised to use an external under-
voltage reset circuit in this case.
In order to prevent unintentional EEPROM writes, a two-state write procedure must be
followed. Refer to the description of the EEPROM Control Register for details of this.
When the EEPROM is read or written, the CPU is halted for two clock cycles before the
next instruction is executed.
The EEPROM Address
Register – EEAR
Bit 7, 6 – Res: Reserved Bits
These bits are reserved bits in the ATtiny15L and will always read as zero.
Bit 5..0 – EEAR5..0: EEPROM Address
The EEPROM Address Register (EEAR) specifies the EEPROM address in the 64 bytes
EEPROM space. The EEPROM data bytes are addresses linearly between 0 and 63.
The initial value of EEAR is undefined. A proper value must be written before the
EEPROM may be accessed.
The EEPROM Data Register –
EEDR
Bit 7..0 – EEDR7..0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to
the EEPROM in the address given by the EEAR Register. For the EEPROM read oper-
ation, the EEDR contains the data read out from the EEPROM at the address given by
EEAR.
Bit
7
65
43
2
1
0
$1E
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
EEAR
Read/Write
R
R/W
Initial vAlue
0
X
Bit
7
65
432
10
$1D
MSB
LSB
EEDR
Read/Write
R/W
Initial Value
0
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