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參數(shù)資料
| 型號： | ATTINY15L-1SI |
| 廠商： | Atmel |
| 文件頁數(shù)： | 41/85頁 |
| 文件大小： | 0K |
| 描述： | IC AVR MCU 1K FLASH 2.7V SO8 |
| 標準包裝： | 95 |
| 系列： | AVR® ATtiny |
| 核心處理器： | AVR |
| 芯體尺寸： | 8-位 |
| 速度： | 1.6MHz |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 6 |
| 程序存儲器容量： | 1KB（512 x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 64 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-SOIC（0.209"，5.30mm 寬） |
| 包裝： | 管件 |
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46
ATtiny15L
1187H–AVR–09/07
ADC Noise Canceler
Function
The ADC features a noise canceler that enables conversion during ADC Noise Reduc-
tion mode (see “Sleep Modes” on page 23) to reduce noise induced from the CPU core
and other I/O peripherals. If other I/O peripherals must be active during conversion, this
mode works equivalently for Idle mode. To make use of this feature, the following proce-
dure should be used:
1.
Make sure that the ADC is enabled and is not busy converting. Single Conver-
sion mode must be selected and the ADC conversion complete interrupt must be
enabled.
ADEN = 1
ADSC = 0
ADFR = 0
ADIE = 1
2.
Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conver-
sion once the CPU has been halted.
3.
If no other interrupts occur before the ADC conversion completes, the ADC inter-
rupt will wake up the MCU and execute the ADC conversion complete interrupt
routine.
The ADC Multiplexer Selection
Register – ADMUX
Bits 7..6 – REFS1..REFS0: Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in Table 19. If these bits
are changed during a conversion, the change will not go into effect until this conversion
is complete (ADIF in ADCSR is set). Whenever these bits are changed, the next
conversion will take 25 ADC clock cycles. If active channels are used, using AVCC or an
external AREF higher than (AVCC - 1V) is not recommended, as this will affect ADC
accuracy. The internal voltage reference options may not be used if an external
reference voltage is being applied to the AREF pin.
Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data
Register. If ADLAR is cleared, the result is right-adjusted. If ADLAR is set, the result is
left-adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately,
regardless of any ongoing conversions. For a complete description of this bit, see “The
Bit
7654
321
0
$07
REFS1
REFS0
ADLAR
–
MUX2
MUX1
MUX0
ADMUX
Read/Write
R/W
R
R/W
Initial Value
0000
000
0
Table 19. Voltage Reference Selections for ADC
REFS1
REFS0
Voltage Reference Selection
00
VCC used as analog reference, disconnected from PB0 (AREF).
01
External Voltage Reference at PB0 (AREF) pin, Internal Voltage
Reference turned off.
10
Internal Voltage Reference without external bypass capacitor,
disconnected from PB0 (AREF).
11
Internal Voltage Reference with external bypass capacitor at PB0 (AREF)
pin.
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