參數(shù)資料
型號(hào): ATTINY24A-SSNR
廠商: Atmel
文件頁數(shù): 7/135頁
文件大?。?/td> 0K
描述: MCU AVR 2KB FLASH 20MHZ 14SOIC
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
tinyAVR Introduction
標(biāo)準(zhǔn)包裝: 1
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 20MHz
連通性: USI
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 12
程序存儲(chǔ)器容量: 2KB(1K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: ATTINY24A-SSNRDKR
104
32015G–AVR32–09/09
AT32AP7001
11.5.10
Reset Controller
The Reset Controller collects the various reset sources in the system and generates hard and
soft resets for the digital logic.
The device contains a Power-On Detector, which keeps the system reset until power is stable.
This eliminates the need for external reset circuitry to guarantee stable operation when powering
up the device.
It is also possible to reset the device by asserting the RESET_N pin. This pin has an internal pul-
lup, and does not need to be driven externally when negated.
Table 11-4 lists these and other reset sources supported by the Reset Controller.
Figure 11-5. Reset Controller block diagram
Reset sources are divided into hard and soft resets. Hard resets imply that the system could
have become unstable, and virtually all logic will be reset. The clock generator, which also con-
trols the oscillators, will also be reset. If the device is reset due to a power-on reset, or reset
occurred when the device was in a sleep mode that disabled the oscillators, the normal oscillator
startup time will apply.
A soft reset will reset most digital logic in the device, such as CPU, HSB, and PB modules, but
not the OCD system, clock generator, Watchdog Timer and RTC, allowing some functions,
including the oscillators, to remain active during the reset. The startup time from a soft reset is
thus negligible. Note that all PB registers are reset, except those in the RTC/WDT. The
MCCTRL and CKSEL registers are reset, and the device will restart using Oscillator 0 as clock
source for all synchronous clocks.
In addition to the listed reset types, the JTAG can keep parts of the device statically reset
through the JTAG Reset Register. See JTAG documentation for details.
NTAE
Reset
Controller
RESET_N
Power-On
Detector
DBR
Watchdog Reset
RC_RCAUSE
Hard Reset
Soft Reset
CPU, HSB,
PBA, PBB
OCD, RTC/WDT
Clock Generato
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