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參數(shù)資料
| 型號(hào)： | AX250-1PQ208 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 2816 CLBS, 154000 GATES, 763 MHz, PQFP208 |
| 封裝： | 0.50 MM PITCH, PLASTIC, QFP-208 |
| 文件頁(yè)數(shù)： | 146/230頁(yè) |
| 文件大小： | 6485K |
| 代理商： | AX250-1PQ208 |
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Axcelerator Family FPGAs
v2.8
2-9
I/O Specifications
Pin Descriptions
Supply Pins
GND
Ground
Low supply voltage.
VCCA
Supply Voltage
Supply
voltage
for
array
(1.5V).
See
Conditions" on page 2-1 for more information.
VCCIBx
Supply Voltage
Supply voltage for I/Os. Bx is the I/O Bank ID – 0 to 7. See
for
more
information.
VCCDA
Supply Voltage
Supply voltage for the I/O differential amplifier and JTAG
and probe interfaces. See "Operating Conditions" on
3.3V.
VCCPLA/B/C/D/E/F/G/H Supply Voltage
PLL analog power supply (1.5V) for internal PLL. There
are eight in each device. VCCPLA supports the PLL
associated with global resource HCLKA, VCCPLB supports
the PLL associated with global resource HCLKB, etc. The
PLL analog power supply pins should be connected to
1.5V whether PLL is used or not.
VCOMPLA/B/C/D/E/F/G/HSupply Voltage
Compensation reference signals for internal PLL. There
are eight in each device. VCOMPLA supports the PLL
associated
with
global
resource
HCLKA,
VCOMPLE
supports the PLL associated with global resource CLKE,
etc. (see Figure 2-2 on page 2-9 for correct external
connection to the supply). The VCOMPLX pins should be
left floating if PLL is not used.
VPUMP
Supply Voltage (External Pump)
In the low power mode, VPUMP will be used to access an
external charge pump (if the user desires to bypass the
internal charge pump to further reduce power). The
device starts using the external charge pump when the
voltage level on VPUMP reaches VIH
1. In normal device
operation, when using the internal charge pump, VPUMP
should be tied to GND.
User-Defined Supply Pins
VREF
Supply Voltage
Reference voltage for I/O banks. VREF pins are configured
by the user from regular I/O pins; VREF pins are not in
fixed locations. There can be one or more VREF pins in an
I/O bank.
Global Pins
HCLKA/B/C/D
Dedicated (Hardwired) Clocks A, B, C
and D
These pins are the clock inputs for sequential modules or
north
PLLs.
Input levels are
compatible
with all
supported I/O standards. There is a P/N pin pair for
support of differential I/O standards. Single-ended clock
I/Os can only be assigned to the P side of a paired I/O.
This input is directly wired to each R-cell and offers clock
speeds independent of the number of R-cells being
driven.
When
the
HCLK
pins
are
unused,
it
is
recommended that they are tied to ground.
CLKE/F/G/H
Routed Clocks E, F, G, and H
These pins are clock inputs for clock distribution
networks or south PLLs. Input levels are compatible with
all supported I/O standards. There is a P/N pin pair for
support of differential I/O standards. Single-ended clock
I/Os can only be assigned to the P side of a paired I/O.
The clock input is buffered prior to clocking the R-cells.
When the CLK pins are unused, Actel recommends that
they are tied to ground.
Figure 2-2 VCCPLX and VCOMPLX Power Supply Connect
1.5V Supply
Axcelerator Chip
0.1f
10f
250
Ω
VCCPLX
VCOMPLX
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AX250-2FG256I | FPGA, 2816 CLBS, 154000 GATES, 870 MHz, PBGA256 |
| AX250-2FG256 | FPGA, 2816 CLBS, 154000 GATES, 870 MHz, PBGA256 |
| AX250-2FG484I | FPGA, 2816 CLBS, 154000 GATES, 870 MHz, PBGA484 |
| AX250-2FG484 | FPGA, 2816 CLBS, 154000 GATES, 870 MHz, PBGA484 |
| AX250-2PQ208I | FPGA, 2816 CLBS, 154000 GATES, 870 MHz, PQFP208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX250-1PQ208I | 功能描述:IC FPGA AXCELERATOR 250K 208QFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Axcelerator 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| AX250-1PQ208M | 制造商:Microsemi Corporation 功能描述:FPGA AXCELERATOR 154K GATES 2816 CELLS 763MHZ 0.15UM 1.5V 20 - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 115 I/O 208PQFP |
| AX250-1PQ896 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX250-1PQ896B | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX250-1PQ896I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
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