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參數(shù)資料
| 型號(hào)： | AX250-FGG256I |
| 廠商： | Microsemi SoC |
| 文件頁(yè)數(shù)： | 168/262頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA AXCELERATOR 250K 256FBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | Axcelerator |
| 邏輯元件/單元數(shù)： | 2816 |
| RAM 位總計(jì)： | 55296 |
| 輸入/輸出數(shù)： | 138 |
| 門數(shù)： | 250000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-FPBGA（17x17） |
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Axcelerator Family FPGAs
Re vi s i on 18
2 - 11
User I/Os2
Introduction
The Axcelerator family features a flexible I/O structure, supporting a range of mixed voltages (1.5 V,
1.8 V, 2.5 V, and 3.3 V) with its bank-selectable I/Os. Table 2-8 on page 2-12 contains the I/O standards
supported by the Axcelerator family, and Table 2-10 on page 2-12 compares the features of the different
I/O standards.
Each I/O provides programmable slew rates, drive strengths, and weak pull-up and weak pull-down
circuits. The slew rate setting is effective for both rising and falling edges.
I/O standards, except 3.3 V PCI and 3.3 V PCI-X, are capable of hot insertion. 3.3 V PCI and 3.3 V PCI-
X are 5 V tolerant with the aid of an external resistor.
The input buffer has an optional user-configurable delay element. The element can reduce or eliminate
the hold time requirement for input signals registered within the I/O cell. The value for the delay is set on
a bank-wide basis. Note that the delay WILL be a function of process variations as well as temperature
and voltage changes.
Each I/O includes three registers: an input (InReg), an output (OutReg), and an enable register (EnReg).
I/Os are organized into banks, and there are eight banks per device—two per side (Figure 2-6 on
page 2-18). Each I/O bank has a common VCCI, the supply voltage for its I/Os.
For voltage-referenced I/Os, each bank also has a common reference-voltage bus, VREF. While VREF
must have a common voltage for an entire I/O bank, its location is user-selectable. In other words, any
user I/O in the bank can be selected to be a VREF.
The location of the VREF pin should be selected according to the following rules:
Any pin that is assigned as a VREF can control a maximum of eight user I/O pad locations in each
direction (16 total maximum) within the same I/O bank.
I/O pad locations listed as no connects are counted as part of the 16 maximum. In many cases,
this leads to fewer than eight user I/O package pins in each direction being controlled by a VREF
pin.
Dedicated I/O pins such as GND and VCCI are counted as part of the 16.
The two user I/O pads immediately adjacent on each side of the VREF pin (four in total) may only
be used as inputs. The exception is when there is a VCCI/GND pair separating the VREF pin and
the user I/O pad location.
The user does not need to assign VREF pins for OUTBUF and TRIBUF. VREF pins are needed
only for input and bidirectional I/Os.
The differential amplifier supply voltage VCCDA should be connected to 3.3 V.
A user can gain access to the various I/O standards in three ways:
Instantiate specific library macros that represent the desired specific standard.
Use generic I/O macros and then use Designer’s PinEditor to specify the desired I/O standards
(please note that this is not applicable to differential standards).
A combination of the first two methods.
Refer to the I/O Features in Axcelerator Family Devices application note and the Antifuse Macro Library
for more details.
2.
Do not use an external resister to pull the I/O above VCCI for a higher logic “1” voltage level. The desired higher logic “1”
voltage level will be degraded due to a small I/O current, which exists when the I/O is pulled up above VCCI.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AX250-FGG256M | 制造商:Microsemi Corporation 功能描述:FPGA Axcelerator Family 154K Gates 2816 Cells 649MHz 0.15um Technology 1.5V 256-Pin FBGA 制造商:Microsemi Corporation 功能描述:FPGA AXCELERATOR 154K GATES 2816 CELLS 649MHZ 0.15UM 1.5V 25 - Trays |
| AX250-FGG484 | 功能描述:IC FPGA 250K 484FPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Axcelerator 標(biāo)準(zhǔn)包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計(jì):221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA（23x23） 其它名稱:220-1241 |
| AX250-FGG484I | 功能描述:IC FPGA AXCELERATOR 250K 484FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Axcelerator 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| AX250-FGG484M | 制造商:Microsemi Corporation 功能描述:FPGA AXCELERATOR 154K GATES 2816 CELLS 649MHZ 0.15UM 1.5V 48 - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 248 I/O 484FBGA |
| AX250-FGG896 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
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