參數(shù)資料
型號: AXDA2700DUV3D
元件分類: 微處理器
英文描述: Microprocessor
中文描述: 微處理器
文件頁數(shù): 60/104頁
文件大?。?/td> 1769K
代理商: AXDA2700DUV3D
48
Signal and Power-Up Requirements
Chapter 9
AMD Athlon XP Processor Model 8 Data Sheet
25175E—November 2002
Preliminary Information
Clock Multiplier
Selection (FID[3:0])
The chipset samples the FID[3:0] signals in a chipset-specific
manner from the processor and uses this information to
determine the correct serial initialization packet (SIP). The
chipset then sends the SIP information to the processor for
configuration of the AMD Athlon system bus for the clock
multiplier that determines the processor frequency indicated
by the FID[3:0] code. The SIP is sent to the processor using the
SIP protocol. This protocol uses the PROCRDY, CONNECT, and
CLKFWDRST signals, that are synchronous to SYSCLK.
For more information about FID[3:0], see “FID[3:0] Pins” on
page 73.
Serial Initialization Packet (SIP) Protocol.
Refer to
AMD Athlon
System Bus Specification
, order# 21902 for details of the SIP
protocol.
9.2
Processor Warm Reset Requirements
Northbridge Reset
Pins
RESET# cannot be asserted to the processor without also being
asserted to the Northbridge. RESET# to the Northbridge is the
same as PCI RESET#. The minimum assertion for PCI RESET#
is one millisecond. Southbridges enforce a minimum assertion
of RESET# for the processor, Northbridge, and PCI of 1.5 to 2.0
milliseconds.
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