![](http://datasheet.mmic.net.cn/300000/BCANPSV2-0_datasheet_16192134/BCANPSV2-0_20.png)
15/Apr/98@11:06
—this line does not form part of the document—
CANLOF
MOTOROLA
xii
CAN PROTOCOL
Rev. 3
LIST OF FIGURES
Figure
Number
Page
Number
TITLE
13-1
13-2
A-1
A-2
A-3
A-4
A-5
A-6
B-1
B-2
B-3
B-4
B-6
C-1
C-2
C-3
C-4
C-5
C-6
C-7
C-8
C-9
C-10
D-1
D-2
D-3
D-4
D-5
D-6
D-7
D-8
D-9
D-10
D-11
D-12
D-13
D-14
D-15
Nominal bit time ....................................................................................................13-1
Bit timing of CAN devices without local CPU ........................................................13-3
MCAN module block diagram................................................................................. A-2
Block diagram of the MCAN interface .................................................................... A-5
MCAN module memory map.................................................................................. A-6
Oscillator block diagram......................................................................................... A-16
Segments within the bit time .................................................................................. A-17
A typical physical interface between the MCAN and the MCAN bus lines............. A-24
TOUCAN block diagram and pinout....................................................................... B-2
Typical CAN system ............................................................................................... B-3
Message buffer structure........................................................................................ B-4
TOUCAN interrupt vector generation ..................................................................... B-20
Int request multiplex timing..................................................................................... B-22
The CAN System ...................................................................................................C-3
User Model for Message Buffer Organization ........................................................C-6
Single 32 bit Maskable Identifier Acceptance Filter ...............................................C-8
Dual 16 bit Maskable Acceptance Filters...............................................................C-9
Quadruple 8 bit Maskable Acceptance Filters........................................................C-10
Sleep Request / Acknowledge Cycle .....................................................................C-14
Clocking Scheme ...................................................................................................C-17
Segments within the Bit Time.................................................................................C-18
Receive/transmit message buffer extended identifier registers..............................C-21
Standard identifier mapping registers ....................................................................C-22
The CAN System ...................................................................................................D-3
User model for message buffer organisation..........................................................D-6
32-bit Maskable Identifier Acceptance Filter ..........................................................D-8
16-bit Maskable Acceptance Filters .......................................................................D-9
8-bit Maskable Acceptance Filters .........................................................................D-10
Sleep Request / Acknowledge Cycle .....................................................................D-14
Clocking Scheme ...................................................................................................D-17
Segments within the Bit Time.................................................................................D-18
MSCAN12 Memory Map........................................................................................D-19
Receive/transmit message buffer extended identifier.............................................D-21
Standard identifier mapping...................................................................................D-21
Identifier acceptance registers (1
ST
bank) .............................................................D-38
Identifier acceptance registers (2
ND
bank).............................................................D-38
Identifier mask registers (1
ST
bank).......................................................................D-38
Identifier mask registers (2
ND
bank)........................................................................D-39
F
.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com