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MOTOROLA
vi
CAN PROTOCOL
Rev. 3
INDEX
TSEG22-TSEG10 – time segment bits
A-17
CBTR0 — MSCAN bus timing reg.
C-27
BPR5 — BPR0
C-27
SJW1, SJW0
C-27
CBTR1 — MSCAN bus timing reg.
SAMP
C-28
TSEG22 — TSEG10
C-28
CCNTRL – MCAN control register
A-7
,
D-26
,
D-27
EIE – error interrupt enable bit
A-8
MODE – undefined mode bit
A-7
OIE – overrun interrupt enable bit
A-8
RIE – receive interrupt enable bit
A-8
RR – reset request bit
A-8
D-26
SPD – speed mode bit
A-8
TIE – transmit interrupt enable bit
A-8
CCOM – MCAN command register
A-9
AT – abort transmission bit
A-11
COMPSEL – comparator selector bit
A-10
COS – clear overrun status bit
A-10
RRB – release receive buffer bit
A-10
RX0, RX1 – receive pin bits
A-9
SLEEP – go to sleep bit
A-10
D-26
TR – transmission request bit
A-11
CIDAC — MSCAN identifier acceptance control reg.
IDAM1 — IDAM0
C-35
IDHIT
C-35
CIDAR0—3 — MSCAN08 identifier acceptance reg.
C-37
AC7 — AC0
C-37
CIDMR0—3 — MSCAN08 identifier mask reg.
AM7 — AM0
C-38
CINT – MCAN interrupt register
A-13
,
D-31
,
D-33
,
D-34
,
D-35
D-36
D-39
,
D-40
EIF – error interrupt flag
A-13
D-31
,
D-32
,
D-33
OIF – overrun interrupt flag
A-13
D-32
D-34
RIF – receive interrupt flag
A-14
,
D-32
TIF – transmit interrupt flag
A-14
,
D-34
WIF – wake-up interrupt flag
A-13
,
D-31
CLKSRC bit in CMCR1
C-26
clock system
MSCAN08
C-16
CMCR0 — MSCAN module control reg.
SFTRES
C-25
SLPAK
C-25
SLPRQ
C-25
SYNCH
C-25
TLNKEN
C-25
CMCR1 — MSCAN module control reg.
C-26
CLKSRC
C-26
LOOPB
C-26
WUPM
C-26
COCNTRL – MCAN output control register
A-19
OCM1, OCM0 – output control mode bits
A-19
compatibility
CAN protocols
7-10
COMPSEL bit in CCOM
A-10
control registers
CBTR0
C-27
CBTR1
C-28
CIDAC
C-35
CMCR0
C-25
CMCR1
C-26
CRFLG
C-29
CRIER
C-31
CTCR
C-34
CTFLG
C-33
CTRL1
B-32
CTRL2
B-34
CTRLO
B-31
PRESDIV
B-34
TIMER
B-35
COS bit in CCOM
A-10
CPU
MSCAN08, wait mode
C-15
CRC field
standard and extended formats
10-6
CRCER bit in STATH, STATL
B-39
CRFLG — MSCAN receiver flag reg.
BOFFIF
C-30
OVRIF
C-30
RERRIF
C-30
RWRNIF
C-29
RXF
C-31
TERRIF
C-30
TWRNIF
C-30
WUPIF
C-29
CRIER — MSCAN receiver interrupt enable reg.
BOFFIE
C-32
OVRIE
C-32
RERRIE
C-31
RWRNIE
C-31
RXFIE
C-32
TERRIE
C-32
TWRNIE
C-31
WUPIE
C-31
CRXERR — MSCAN receive error counter
C-36
CSTAT – MCAN status register
A-11
BS – bus status bit
A-11
DO – data overrun bit
A-12
ES – error status bit
A-11
RBS – receive buffer status bit
A-13
RS – receive status bit
A-12
TBA – transmit buffer access bit
A-12
TCS – transmission complete status bit
A-12
TS – transmit status bit
A-12
CTCR — MSCAN transmitter control reg.
ABTRQ2 — ABTRQ0
C-34
TXEIE2 — TXEIE0
C-34
CTFLG — MSCAN transmitter flag reg.
C-33
ABTAK2 — ABTAK0
C-33
TXE2 — TXE0
C-33
CTRL0 — TOUCAN control reg. 0
BOFF
B-31
ERR
B-31
RXMD[1,0]
B-31
TXMD[1,0]
B-32
CTRL1 — TOUCAN control reg. 1
LBUF
B-33
PSEG[2:0]
B-33
SAMP
B-32
TSYNC
B-32
F
.
Freescale Semiconductor, Inc.
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