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| 型號： | BR1570 |
| 英文描述： | WarpLink Reference Design Platform |
| 中文描述： | WarpLink參考設(shè)計平臺 |
| 文件頁數(shù)： | 22/24頁 |
| 文件大小： | 492K |
| 代理商： | BR1570 |
WarpLink Reference Design Platform
22
For More Information On This Product,
Go to: www.freescale.com
SUMMARY AND CONCLUSIONS
The Motorola WarpLink Reference Design Platform demonstrates the capabilities of the WarpLink 2.5 Quad SERDES device. The device
was operated at wire speed of 3.125 Gbd to provide an aggregate speed of 10Gbps per device. The device’s pre-emphasis/equalization
feature proved indispensable for data transfer at gigabit wire speeds over long interconnects. In particular, WarpLink 2.5 Quad has
demonstrated the ability to operate at, and beyond the XAUI specification of 3.125 Gbd over 50cm long channels.
The WarpLink Reference Design Platform is built with common design practices, components, and PCB material (FR-4). Unrealistic and
expensive gigabit design requirements - such as blind vias, via drill-back, bottom-layer-only routing, and low dielectric constant PCB
materials - were not required.
Using a fully matured simulation and design methodology, NESA implemented a full end-to-end gigabit simulation matrix of cases. The
currently available SERDES model for WarpLink 2.5 Quad was verified to emulate actual measured results. Using this modeling strategy,
areas of risk for the gigabit links were identified and properly addressed while still in the design phase.
The Motorola WarpLink Reference Design Platform has shown that 3.125 Gbd SERDES technology is a reality, with readily available
support. Proven Reference Design Platforms and confirmed WarpLink I/O simulation models are available from Motorola.
ACKNOWLEDGEMENTS
This white paper was prepared as a joint effort by Quang Xuan Nguyen of the Motorola WarpLink design team and Dr. Edward Sayer 3rd
from North East Systems Associates Inc. (NESA, www.nesa.com). NESA was contracted by Motorola to do the design, perform simulations
and define the layout rules for the reference backplane. Their expertise lies in the area of the practical design and manufacturing
techniques required for high performance systems and backplanes.
Additional thanks go to Michael Baxter, NESA and Thecla Chomicz, Motorola for their technical expertise and assistance in performing the
extensive passive and active measurements presented in this paper.
F
Freescale Semiconductor, Inc.
n
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