參數(shù)資料
型號： BT865AKPF
英文描述： Color Encoder Circuit
中文描述： 顏色編碼器電路
文件頁數(shù)： 55/76頁
文件大?。?/td> 1050K
代理商： BT865AKPF
Bt864A/865A
2.0 Internal Registers
YCrCb to NTSC/PAL Digital Video Encoder
2.5 Programming Detail
100138B
Conexant
2-5
CBSWAP
0 = Normal pixel sequence.
1 = The Cb and Cr pixels can be swapped at the input of the pixel port. Refer to the pixel sequence section for
more information.
PORCH
0 = Front and back porch timing conforms to ITU-RBT.470-3. Front porch is 1.5 μs and back porch is 9.4 μs
for M-systems or 10.5 μs for PAL-systems. The active video region is therefore smaller than the 720 pixels
specified in CCIR601.
1 = Redefine porch timing per CCIR601. This setting allows the full picture with 720 pixels to be encoded by
using a portion of both the front and back porch for active video.
CCF2B1[7:0]
This is the first byte of closed-caption information for the FIELD 2, line 284 for NTSC or line 335 for PAL. Data
is encoded LSB first.
CCF2B2[7:0]
This is the second byte of closed-caption information for the FIELD 2, line 284 for NTSC or line 335 for PAL.
Data is encoded LSB first.
CCF1B1[7:0]
This is the first byte of closed-caption information for the FIELD 1, line 21 for NTSC or line 22 for PAL. Data is
encoded LSB first.
CCF1B2[7:0]
This is the second byte of closed-caption information for the FIELD 1, line 21 for NTSC or line 22 for PAL. Data
is encoded LSB first.
HSYNCF[9:0]
HSYNCR[9:0]
When ADJHSYNC is enabled, these 10 bit registers can be used to program the placement of the falling and
rising edges of HSYNC* relative to the internal horizontal pixel clock. This variable horizontal timing mode is
available in master mode only. For more detail, see the Pixel Input Timing section.
SYNCDLY
0 = Normal sync timing.
1 = Delayed sync timing.
FIELDI
0 = A
“
1
”
on FIELD pin indicates a FIELD 2.
1 = A
“
1
”
on FIELD pin indicates a FIELD 1.
SYNCDIS
0 = Normal HSYNC* operation.
1 = Disable HSYNC* edges during VBI (master mode only).
ADJHSYNC
0 = Output hsync pulse on HSYNC*. The standard hsync pulse falls at the start of a new line and remains low
for 4.7
μ
s.
1 = Output a programmable hsync pulse on HSYNC*. By programming HSYNCR and HSYNCF, HSYNC* can
rise and fall at any desired time during each line.
SETMODE
This bit is ignored in master mode (automatic mode detection is not applicable in slave mode).
0 = By default, in slave mode, the video mode is automatically detected. This is further explained in the SLAVE
mode section.
1 = Override automatic mode-detection in slave mode. The mode will be set according to the VIDFORM[3:0],
NONINTL, and SQUARE register bits.
SETUPDIS
0 = Setup on. The 7.5 IRE setup is enabled for active video lines.
1 = Setup off. The 7.5 IRE setup is disabled.
VIDFORM[3:0]
Configures the device for various worldwide video formats
D5
D4
D3
D2
Format
Typical Market
0
0
0
0
NTSC normal
USA/Japan
0
0
1
0
NTSC-60 Hz
(1)
USA
–
HDTV
1
1
0
0
PAL-M normal
Brazil
1
1
1
0
PAL-M
–
60 HZ
Brazil - HDTV
1
0
0
1
PAL-BDGHIN
W. Europe
1
1
0
1
PAL-Nc
Argentina
NOTE(S):
(1)
SCRESET must be
“
1
”
.
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