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Bt864A/865A
3.0 PC Board Considerations
YCrCb to NTSC/PAL Digital Video Encoder
3.5 Applications Information
100138B
Conexant
3-7
3.5.3 Mutual Inductance Concerns
The designer should prevent a situation where signals from other devices next to
the encoder cause the crystal to generate faulty clocks.
The Conexant encoder and any associated crystal that drives the CLK input
should physically be placed as far as possible from signal lines with excessive
currents. Excessive currents are defined to be greater than the Total Supply
Current figure listed in
Table 4-3
.
In some systems, there are signal lines for controlling motors, LEDs, and
thermal heads. When a large current flows through these traces problematic noise
can result from the phenomenon of mutual inductance (See
Figure 3-3
).
Figure 3-3. Example of Mutual Inductance
3.5.4 Reset Precautions
The user should make the length of the traces connected to the RESET* input pin
as short as possible. In addition, Conexant recommends that a 0.1 μF capacitor be
connected across the RESET* input pin and the digital ground pins (GND) for
decoupling purposes.
All of Bt864A/865A
’
s programmable register bits can be reset through
software (i.e., setting register bit SRESET= 1). Furthermore, both the
Bt864A/865A
’
s registers and timing can be reset by a low pulse of at least 0.05 μs
(>1 complete period of CLK) input directly to RESET*. If noise, having a pulse
width close to 0.05 μs, is inadvertently input to RESET*, it could cause the
encoder to unintentionally reset the subcarrier phase and/or the horizontal and
vertical counters (see
Figure 1-9
). This type of timing error could cause faulty
system operation (see
Figure 3-4
).
CLK
GND
Large Current
M
Figure 3-4. Wiring for the Reset Input Pin
RESET*
GND
0.1 μF
Short as Possible