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參數(shù)資料
| 型號： | BU-61703F4-112 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 X 1 INCH, 0.155 INCH HEIGHT, CERAMIC, FP-72 |
| 文件頁數(shù)： | 29/52頁 |
| 文件大?。?/td> | 367K |
| 代理商： | BU-61703F4-112 |
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35
SIMPLE SYSTEM INTERFACE
FIGURE 15 illustrates the capability of the SSRT to interface to
a system with no host processor in burst mode. In this example,
only one set of external latches is needed to buffer the data
words written by the SSRT to the external system. In burst mode,
all received data words are stored in the internal FIFO until the
last word is received. At this point, the SSRT will transfer the
entire contents of the FIFO to the system if the message is vali-
dated. In this case,
will be driven low for two clock cycles
following the burst transfer cycle.
If the received message is not valid, the FIFO data will not be
transferred to the external system and
will remain high.
GBR
FIGURE 15. SSRT-TO-SIMPLE SYSTEM INTERFACE (Shown for BURST MODE)
D15-D0
Write
Address
Decoder
Read
Address
Decoder
LATCH
TRI-STATE
BUFFER
TRI-STATE
BUFFER
EN
TRI-STATE
BUFFER
EN
L-BRO, T/R, SA4-0,
WC/CWC4-0
MEMWR
DISCRETE
DIGITAL
INPUTS
DISCRETE
DIGITAL
OUTPUTS
AUTO-
CONFIGURATION
(OPTIONAL)
RTACTIVE
DTACK
AUTO_CFG
MEMOE
BU-61703/5
SSRT
EN
Clock
Oscillator
CLK-IN
RTAD4-0, RTADP
MSTCLR
+5V
RT
ADDRESS
BUS A
BUS B
DTGRT
+5V
相關(guān)PDF資料 |
PDF描述 |
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| BU-61703F4-122Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61703F4-132S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61703F4-132Z | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61703F4-142L | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61703F4-142Z | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
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