參數(shù)資料
型號(hào)： BU-61703F4-112
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝： 1 X 1 INCH, 0.155 INCH HEIGHT, CERAMIC, FP-72
文件頁(yè)數(shù)： 41/52頁(yè)
文件大小： 367K
代理商： BU-61703F4-112
46
DESCRIPTION
Remote Terminal Fail. This two-state output signal will be asserted low following a failure of the built-in self-test
performed following power turn-on or as the result of the receipt of an Initiate self-test mode command. The
built-in off-line self-test includes tests of the Manchester encoder and decoders, transmitter failsafe timer, and
RT protocol logic.
In addition, RTFAIL will be asserted low following a failure of the on-line loop test for any non-broadcast mes-
sage. The on-line loop test verifies the validity of the received version of all transmitted words (sync,
Manchester encoding, bit count, parity), and includes a bit-by-bit comparison and verification of the last trans-
mitted word.
If asserted to logic "0", RTFAIL will clear to logic "1" when the SSRT begins transmission of its status word in
response to a subsequent valid non-broadcast message.
Message Error. Active low level two-state output signal used to flag to the external system that there was a
message error on the 1553 bus communication (word, gap, or word count error) for a particular message. This
output goes low upon detecting the error and is reset following the receipt of the next valid command word (to
the RT) from the 1553 bus, or if MSTCLR is asserted low. If this output goes low, all further servicing of the
current message is aborted.
Good Block Received. Low level two-state output pulse (2 clock cycles wide) that is used to indicate to the
external system that a valid, legal, non-mode receive command with the correct number of valid data words
has been received and transferred to the external system.
For non-burst mode, this pulse will occur after the last data word is transferred. Assuming a DTREQ-to-DTGRT
time of 0, this will be approximately 4 s following the mid-parity bit crossing of the last received data word.
For burst mode, the GBR pulse will begin synchronous with the rising edge of DTACK at the end of the burst
write transfer.
RTFAIL (O)
MSG_ERR (O)
GBR (O)
58
28
60
SIGNAL
RT ACTIVITY AND MESSAGE STATUS INDICATORS
RT Active. This signal will be low (logic "0") following power turn-on, and when the SSRT is reading its Auto-
configure word or is performing its internal self-test. After the self-test passes, or if the Auto-configure option is
not used, or if Auto-configure is used but bit 5 of the Auto-configure word is logic "1" (meaning for the RT to
always go online), RTACTIVE will then transition to logic "1". When this occurs, the SSRT will begin processing
messages over the 1553 bus.
If Auto-configure is enabled, and bit 5 of the Auto-configure word is logic "0" and the self-test fails, then RTAC-
TIVE will remain at logic "0". In this case, the SSRT will remain offline and not process any 1553 messages.
A failed self test will cause RTFAIL_L to be asserted low (logic “0").
If the auto-configure option is used, the external system should enable the configuration bits on D5-D0 when
RTACTIVE and DTACK are both outputting logic "0".
RTACTIVE
56
PIN
In-command. This two-state output is asserted low whenever a message is being processed by the SSRT.
INCMD
25
DESCRIPTION
Transmitter inhibit input for the MIL-STD-1553 transmitters. For normal operation, this input should be connect-
ed to logic "0". To force a shutdown of the Channel A and Channel B transmitters, a value of logic "1" should
be applied to this input.
TX_INH (I)
59
Broadcast Enable. If this input is logic "1", the SSRT will recognize RT address 31 as the broadcast address. If
this input is logic "0", the SSRT will not recognize RT ad dress 31 as the broadcast address; however, in this
configuration, RT address 31 may be used as a standard RT address.
BRO_ENA (I)
63
Auto-configure input. If connected to logic "1", then the auto-configure option is disabled, and the six configura-
tion parameters revert to their default values as listed in Table 2. Note that the default condition for each config-
uration parameter is enabled (for the MIL-STD-1553A/B protocol selection, -1553B is the default).
If AUTO_CFG is connected to logic "0", then the configuration parameters are transferred over D5-D0 during a
DMA read data transfer, when RTACTIVE and DTACK are logic "0", following MSTCLR transitioning from logic
"0" to logic "1". Each of the configuration parameters is enabled if the SSRT reads a value of logic "1" for the
respective data bit.
AUTO_CFG (I)
70
Master Clear. Negative true Reset input, asserted low following power turn-on. When coming out of a “reset”
condition, note that the risetime of MSTCLR must be less than 10 s.
MSTCLR (I)
2
SIGNAL
CONTROL INPUTS
PIN
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