參數(shù)資料
型號: BU-61703F4-172Y
廠商: DATA DEVICE CORP
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝: 1 X 1 INCH, 0.155 INCH HEIGHT, CERAMIC, FP-72
文件頁數(shù): 20/52頁
文件大?。?/td> 367K
代理商: BU-61703F4-172Y
27
TABLE FOR FIGURE 11. SSRT DMA READ TIMING
VALUE @ 5 Volts
VALUE @ 3.3 Volts
REF
DESCRIPTION
CLOCK
FREQUENCY
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
t1
CLOCK IN rising to DTREQ low
ALL
40
ns
t2
DTREQ (low)-to-DTGRT delay time
ALL
10
s
20 MHz
60
ns
16 MHz
85
ns
12 MHz
127
ns
t3
CWC setup time prior to MEMOE falling
10 MHz
160
ns
t4
DTGRT low setup prior to CLOCK IN rising
ALL
10
ns
20 MHz
100
105
ns
16 MHz
113
118
ns
12 MHz
133
138
ns
t5
DTGRT falling to DTACK low
10 MHz
150
155
ns
t6
CLOCK IN rising to DTACK low
ALL
40
ns
t7
DTGRT hold time following DTACK falling
ALL
30
ns
20 MHz
200
ns
16 MHz
250
ns
12 MHz
333
ns
t8
DTACK low pulse width
10 MHz
400
ns
t9
CLOCK IN rising to MEMOE low
ALL
40
ns
20 MHz
150
ns
16 MHz
188
ns
12 MHz
250
ns
t10
MEMOE low pulse width
10 MHz
300
ns
20 MHz
80
70
ns
16 MHz
105
95
ns
12 MHz
146
136
ns
t11
Time for input data to become valid
following falling edge of MEMOE
10 MHz
180
170
ns
t12
Data input hold time following CLOCK IN
rising (see Note)
ALL
30
ns
t13
CLOCK IN rising to DTREQ, DTACK, and
MEMOE high
ALL
30
40
ns
Note:
The SSRT’s data sampling time occurs one clock cycle prior to the rising edge of MEMOE.
相關(guān)PDF資料
PDF描述
BU-61703F4-172 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61703F4-182S 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61703F4-192S 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
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