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| 型號： | BU-61703F4-172Y |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 X 1 INCH, 0.155 INCH HEIGHT, CERAMIC, FP-72 |
| 文件頁數(shù)： | 3/52頁 |
| 文件大小： | 367K |
| 代理商： | BU-61703F4-172Y |
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11
TABLE FOR FIGURE 3. RT RECEIVE COMMAND TIMING (BURST MODE)
RESPONSE TIME
REF
DESCRIPTION
CLOCK
FREQUENCY
MIN
TYP
MAX
UNITS
t1
Mid-parity crossing of received command word delay to
SA4-SA0, L-BRO, T/R Bit, and WC/MC valid
ALL
1.5
s
t2
Mid-parity crossing of received command word delay to
falling edge of INCMD
ALL
2
s
t3
Mid-Parity crossing of receive command word delay to
MSG_ERR and HS_FAIL rising
ALL
1.5
s
t4
ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time
from SA4-SA0, L-BRO, T/R, and CWC/MC valid
ALL
400
ns
t5
L_BRO, T/R, SA4-0, and WC/MC4-0 valid prior to INCMD
low.
ALL
500
ns
t6
ILLEGAL, SRV_RQST, SSFLAG, BUSY hold time following
falling edge of INCMD
ALL
300
ns
t7
Mid-parity crossing of first data word to WC/CWC valid data
of 1Fh
ALL
1
s
t8
Duration of WC/CWC data value of 1Fh
ALL
200
ns
t9
RT Response time.
ALL
4
6.5
7
s
t10
CWC transition to next word following mid-parity of
subsequent received data words.
ALL
1
s
t11
Mid-parity crossing of last data word to DTREQ falling edge
(requesting data word burst write transfer)
ALL
4
4.5
5.25
s
t12
Mid-Sync crossing of Status response to RT_FAIL rising
ALL
1.5
s
t13
CWC valid following falling edge of DTREQ
ALL
30
ns
20 MHz
100
ns
16 MHz
125
ns
12 MHz
167
ns
t14
GBR pulse width (see Note 1)
10 MHz
200
ns
t15
Mid-parity crossing of status word to INCMD rising
ALL
3
s
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