參數(shù)資料
型號： BU-62743
英文描述： MIL-STD-1553 Components |PCI-Enhanced Mini-ACE?
中文描述： 符合MIL - STD - 1553器件|的PCI增強迷你ACE論壇？
文件頁數(shù)： 44/56頁
文件大?。?/td> 368K
代理商： BU-62743
44
Data Device Corporation
www.ddc-web.com
BU-62743/62843/62864
A-03/03-1M
The PACE responds to the first read with a Retry. By PCI rules
the master must repeat the same exact request until it com-
pletes.This is shown by the master's second read attempt, which
also produces a Retry. Each repeated read request from the
master will be target terminated with a Retry until the data from
the enqued Delayed Read Request (DRR) is present in the
PACE's PCI interface.The successful completion is shown at the
third read request, which produces a Disconnect with Data.
This process applies to any memory read from legal address
space OTHER than the PCI-ACE interface registers at BAR1 off-
set 800-81Ch.
Note that one of the conditions for enquing a DRR is that the
write FIFO must be empty. For efficient use of PCI bus band-
width, the driver software should be written such that it checks
the FIFO condition (BAR1 800-81CH registers are directly read-
able, bypassing the DRR mechanism) before reading from the
other PACE locations.If the FIFO is not empty (BAR1 800h bit 30
is the FIFO not empty flag) and a read is attempted, the bus
master will be using PCI bandwidth repeating the read request
while the FIFO empties, BEFORE the read request is actually
enqued as a DRR.
When reading ACE memory (BAR0), any combination of byte
enables is supported, but the PACE will drive the entire word
onto the AD lines when only a single byte enable in the word is
asserted.
When reading ACE registers (BAR 00-FCh), byte enable combi-
nations where only a single byte within a word is requested will
cause the PACE to terminate the transaction with a target abort.
The PACE will drive all zeros onto the AD lines if only the upper
word byte enables or no byte enables are asserted.
With relation to actual timing, PCI double word reads of ACE
memory (BAR0) will take longer to complete than single word
ACE memory reads because the internal ACE memory data path
is 16 bits wide. In addition, read cycles will take longer to com-
plete with slower ACE clocks. See TABLE 63 for min/max formu-
las for calculating completion time for the various types of reads.
The third case returns all zeroes and is shown only for com-
pleteness.
The following examples have the same conditions: PCI clock =
33MHz, ACE clock = 16MHz, no ACE contention.
Single word read
Min time = 8 x 30 nS + 5 x 62.5 nS = 552.5 nS
Max time = 10 x 30nS + 6 x 62.5 nS = 675 nS
Double word read
Min time = 13 x 30 nS + 11 x 62.5 nS = 1077.5 nS
Max time = 16 x 30nS + 14 x 62.5 nS = 1167.5 nS
In addition, see TABLE 64 for the amount of ACE clocks that
should be added for maximum time if the ACE is active.
Enhanced CPU access enabled, single word xfer
3
Enhanced CPU access enabled, double word xfer
6
Enhanced CPU access disabled, single word xfer
67
Enhanced CPU access disabled, double word xfer
74
TABLE 64. ADDITIONAL DRR DELAY FOR
CONTESTED ACE RAM ACCESS
ACE OPERATING MODE
MAXIMUM
ADDITIONAL
ACE CLOCKS
The Enhanced CPU access is controlled by bit 14 of Configuration Register #6.
ACE memory (BAR0),
double word
13 x PCI_CLKperiod +
11 x ACE_CLKperiod
ACE memory (BAR0)
single word or ACE
register (BAR1, dou-
ble word or lower
word)
8 x PCI_CLKperiod +
5 x ACE_CLKperiod
No CBEN# asserted
or ACE register
(BAR1) upper word
3 x PCI_CLKperiod
TABLE 63. MIN/MAX DELAYED READ FORMULAS
TYPE OF READ
MIN TIME FORMULA
16 x PCI_CLKperiod +
14 x ACE_CLKperiod
10 x PCI_CLKperiod +
6 x ACE_CLKperiod
3 x PCI_CLKperiod
MAX TIME FORMULA
FIGURE 17 illustrates a 16 Dword (32 word) PCI memory write
burst, with the write FIFO empty (or with enough free space to
absorb the 16 Dwords in the FIFO).The write FIFO accepts PCI
memory writes to the ACE memory (BAR0) and ACE registers
(BAR1 offset 00h - FCh). It does not accept writes to the PCI
interface registers at BAR1 offset 800-81Ch.Writes to the BAR1
800-81Ch space go directly into the PCI interface registers. The
32 byte write shown could be an entire 1553 message being writ-
ten to ACE memory.
Writes into the BAR 0 space must be word or Dword. If
only one byte enable is asserted in a word, the PACE termi-
nates the transaction with a Target-Abort.
Writes into the BAR 1 00-FCh space must be word or
Dword. If only one byte enable is asserted in a word, the
PACE terminates the transaction with a Target-Abort. Since
the ACE registers in this space are really 16 bit registers
packed into the lower word of a 32 bit structure, only lower
word or Dword writes transfer bits into these ACE registers.
In addition, as per PCI spec, a Memory Write and
Invalidate (C/BE[3:0]# = Fh) command will be aliased to the
basic Memory Write command and the timing diagram would
look the same as FIGURE 17.
相關PDF資料
PDF描述
BU-62843 MIL-STD-1553 Components |PCI-Enhanced Mini-ACE?
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相關代理商/技術參數(shù)
參數(shù)描述
BU-62843 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |PCI-Enhanced Mini-ACE?
BU-62864 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |PCI-Enhanced Mini-ACE?
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