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參數(shù)資料
| 型號(hào)： | BU-65743F8-100 |
| 廠商： | DATA DEVICE CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
| 封裝： | 0.880 INCH, CERAMIC, QFP-80 |
| 文件頁(yè)數(shù)： | 37/75頁(yè) |
| 文件大?。?/td> | 532K |
| 代理商： | BU-65743F8-100 |
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42
Data Device Corporation
www.ddc-web.com
BU-65743/65843/65863/65864
D-06/04-0
mini-ACE" even though the 1553 terminal function is really an
enhanced mini-ACE. When reference is made to ACE memory
(BAR0) or ACE registers (BAR1 00-FCh) these functions are
part of the ACE portion of the die. These ACE functions are
accesed via the write FIFO (for writes) and delayed read request
logic (for reads). The "PCI interface registers" (BAR1 800-81Ch)
are part of the PCI interface portion of the die and are written and
read directly from the PCI bus, without use of the write FIFO or
delayed read request logic.
The PCI Mini-ACE Mark3/Micro-ACE TE's basic PCI transaction
takes 3 PCI clocks, on top of the command phase. For example,
a single write to any location within the PCI Mini-ACE
Mark3/Micro-ACE TE's memory space takes 4 PCI clocks, as
shown in FIGURE 12. Note that this is a single write, not an
attempted burst write: FRAME# is not held asserted by the mas-
ter. Also note that a write to the ACE registers or ACE memory is
actually a write into the write FIFO whereas a write to the PCI
interface registers (BAR1 800-81Ch) is a write to the registers
themselves.
PCI
"MASTER"
CH. A
TX/RXA
CH. B
TX/RXB
RTAD0-RTAD4
RT
ADDRESS,
PARITY
RTADP
AD0-AD31
Vcc/GND
OSCILLATOR
PAR
C/BE[0]#-C/BE[3]#
PCI
Mini-ACE
Mark3/
Micro-ACE
TE
"Target"
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
INTA#
TAG_CLK
SSFLAG/EXT_TRIG
INCMD/MCRST
SERR#
PERR#
PCI_CLK
MSTCLR (RST#)
RT_AD_LAT
TX_INH_A/B
FIGURE 11. PCI INITIATOR TO PCI MINI-ACE MARK3/MICRO-ACE TE TARGET INTERFACE
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