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| 型號(hào)： | BU-66318G0-110 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PQFP208 |
| 封裝： | 28 X 28 MM, 1.40 MM HEIGHT, LQFP-208 |
| 文件頁(yè)數(shù)： | 19/32頁(yè) |
| 文件大小： | 278K |
| 代理商： | BU-66318G0-110 |
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Data Device Corporation
www.ddc-web.com
BU-66318
B-09/05-0
TABLE 28. PCI BUS SYSTEM SIGNALS
SIGNAL NAME
PIN
DESCRIPTION
PCI_CLK_IN (I)
172
RST# (I)
88
Clock input. The rising edge of this signal is the reference upon which all other clock signals are based, with
the exception of RST# and INTA#. The maximum frequency accepted is 33 MHz and the minimum is 0 Hz.
Reset. This signal is used to bring all other signals within this device, and on the local bus, to a known,
consistent state. All PCI bus interface output signals are not driven (tri-stated), and open drain signals are
floated.
TABLE 29. PCI BUS CONTROL SIGNALS
SIGNAL NAME
PIN
DESCRIPTION
FRAME#(I)
25
IRDY#(I)
27
TRDY#(O)
34
STOP#(O)
41
IDSEL(I)
13
DEVSEL#(O)
33
PERR#(O)
40
SERR#(O)
42
INTA#(O)
15
Frame. This signal is driven by the current bus master and identifies both the beginning and duration of a
bus operation. When FRAME# is first asserted, it indicates that a bus transaction is beginning and that
valid addresses and a corresponding bus command are present on the AD[31:0] and C/BE[3:0] lines.
FRAME# remains asserted during the data transfer portion of a bus operation and is deasserted to signify
the final data phase.
Initiator Ready. This signal is sourced by the bus master and indicates that the bus master is able to com-
plete the current data phase of a bus transaction. For write operations, it indicates that valid data is on the
AD[31:0] pins. Wait states occur until both TRDY# and IRDY# are asserted together.
Target Ready. This signal is sourced by the selected target and indicates that the target is able to complete
the current data phase of a bus transaction. For read operations, it indicates that the target is providing
valid data is on the AD[31:0] pins. Wait states occur until both TRDY# and IRDY# are asserted together.
Stop. The Stop signal is sourced by the selected target and conveys a request to the bus master to stop
the current transaction.
Initialization Device Select. This pin is used as a chip select during configuration read or write operations.
Device Select. This signal is sourced by an active target upon decoding that its address and bus com-
mands are valid. For bus masters, it indicates whether any device has decoded the current bus cycle.
(The BU-66318 operates as a target agent only)
Parity Error. This pin is used for reporting parity errors during the data portion of the bus transaction for all
cycle except a Special Cycle. It is sourced by the agent receiving data and driven active two clocks follow-
ing the detection of an error. This signal is driven inactive (high) two clocks prior to returning to the tri-state
condition.
System Error. This pin is used for reporting address parity errors, data parity errors on Special Cycle com-
mands, or any other condition having a catastrophic system impact.
Interrupt A. This pin is a level sensitive, active low interrupt to the host.
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