- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄223464 > BU-66318G0-110 (DATA DEVICE CORP) 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PQFP208 PDF資料下載
參數(shù)資料
| 型號： | BU-66318G0-110 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PQFP208 |
| 封裝： | 28 X 28 MM, 1.40 MM HEIGHT, LQFP-208 |
| 文件頁數(shù)： | 3/32頁 |
| 文件大小： | 278K |
| 代理商： | BU-66318G0-110 |
第1頁第2頁當前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
11
Data Device Corporation
www.ddc-web.com
BU-66318
B-09/05-0
TABLE 12. FAILSAFE MODE
BIT 17
FAILSAFE MODE
0
OFF
0
1
RETRY
HALT
1
SKIP
BIT 16
0
1
0
1
TABLE 11. SETUP DELAY
BIT 29
SETUP DELAY
0
0 (default) Data Setup = X clocks
0
1
1 Data Setup = X + 1 clocks
2 Data Setup = X + 2 clocks
1
3 Data Setup = X + 3 clocks
BIT 28
0
1
0
1
DRR HOLD: Default is '0'. When = '0', delayed read request is
discarded if ACE-Bridge has obtained requested data and a dif-
ferent transaction is requested.
When = '1', delayed read
request is held until master repeats original request or timeout
occurs.
VECTOR IRQ DISABLE: Default is '0'. When VECTOR IRQ
DISABLE = '0', the 16 bits of interrupt field act as a vector - that
is, all 16 bits are written to '0' or '1' corresponding to the input
data of the current write operation. When VECTOR IRQ DIS-
in the 16 bit interrupt field is set to '1', it cannot be written back
to '0'. The interrupt recipient clears bits only upon a read.
SETUP DELAY FOR LOCAL BUS: Data setup delay (TABLE 11) is
expressed in the number of clock cycles prior to control signal.
The Control signal = strobe for an ACE write or
CS for a BAR2 RAM write or
B_RDY for a local processor read
(In all 3 cases, data is driven by the ACE-Bridge onto the local
data bus.)
Note: X will vary depending upon the type of transfer (ACE write,
RAM write, local proc read), whether data is changing from the
last transfer, and whether transfer is an upper word or lower
word transfer.
LOCAL PROCESSOR INTERRUPT ENABLE: Enables PCI
interrupt if any of the local_irq_vec bits are set [reg0, 15:0]
ACE INTERRUPT ENABLE: These bits must set for any ACEs
that are present that need to generate PCI interrupts, in addition
to enabling the appropriate interrupts in the ACEs themselves.
BAR1 DRR DATA DISCARD INTERRUPT ENABLE: Enables
interrupt to occur on a BAR1 delayed read timeout.
FAILSAFE INTERRUPT ENABLE: When set to a 1, an interrupt
is generated if not in FAILSAFE OFF mode and a FAILSAFE
error is detected.
FAILSAFE INTERRUPT AUTOCLEAR ENABLE: If set, causes
interrupt and the Failsafe Error bit (REG0-bit 22) to be cleared
whenever upper word of REG0 is read by the PCI MASTER.
FAILSAFE MODE: Failsafe Errors occur when either an ACE or
the Local Processor fail to assert a hand-shake signal (e.g. ACE
Ready or Bus Grant) within 1 millisecond (programmable) of
when the Strobe or Request signal is asserted. If a failsafe error
occurs in any failsafe mode except FAILSAFE OFF, an interrupt
will be generated only if the FAILSAFE INTERRUPT ENABLE
has been previously set, and the FAILSAFE ERROR bit in REG0
will be set whether the FAILSAFE INTERRUPT ENABLE has
been set or not. In FAILSAFE OFF mode, a FAILSAFE interrupt
will not occur (even if it has been enabled) and the FAILSAFE
ERROR bit will not be set. There are four possible FAILSAFE
Modes. They are shown in TABLE 12.
00-FAILSAFE OFF: The ACE-Bridge will wait indefinitely for the
transaction to complete. The local bus could hang as a result.
The ACE-Bridge will load any subsequent writes into an internal
FIFO and respond normally on the PCI bus until it is full. Then it
will respond with PCI retries. If Bus Grant or ACE READY final-
ly occurs, the initial transfer and all transfers pending in the FIFO
will be completed.
01-FAILSAFE RETRY: The ACE-Bridge will retry the transfer on
the local bus when the FAILSAFE timer times out. When Bus
Grant or ACE READY occurs, the retried request is completed
along with any pending requests in the FIFO.
10-FAILSAFE HALT: Once the FAILSAFE timer times out, all
future PCI transfers will be terminated with a target abort until the
PCI master clears the interrupt. When local bus access is grant-
ed, it will complete the first request only, since no subsequent
requests are loaded into the FIFO.
11-FAILSAFE SKIP: Once the FAILSAFE timer times out, the
current transaction is discarded or skipped and the next transac-
tion, whether a stored write in the FIFO or a new transaction, will
be attempted. ACE-Bridge will keep skipping down through the
FIFO entries every time the timer times out and restarts.
INTERRUPT VECTOR FROM PCI: Writing to this location by the
PCI Master causes a local processor interrupt only if at least one
of the bits (15-0) is a '1'.
Reading this location by the local
processor clears the register. The PCI Master may read back
相關PDF資料 |
PDF描述 |
|---|---|
| BU2294AF | 67.735842 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| BU3076HFV-TR | 67.5 MHz, OTHER CLOCK GENERATOR, PDSO6 |
| BU6836 | PCMCIA BUS CONTROLLER, PBGA256 |
| BU7346GUL | 38 MHz, OTHER CLOCK GENERATOR, PBGA6 |
| BUF01900AIDRCR | SPECIALTY ANALOG CIRCUIT, PDSO10 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| BU6650NUX | 制造商:ROHM 制造商全稱:Rohm 功能描述:3ch CMOS LDO Regulators |
| BU6650NUX_11 | 制造商:ROHM 制造商全稱:Rohm 功能描述:3ch CMOS LDO Regulators |
| BU6650NUX-TR | 功能描述:低壓差穩(wěn)壓器 - LDO LDO REG 0.2A 8PIN 2.8V 2.8V 1.8V RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| BU6651NUX | 制造商:ROHM 制造商全稱:Rohm 功能描述:High-speed Load Response Full CMOS LDP Regulators |
| BU6651NUX-TR | 功能描述:低壓差穩(wěn)壓器 - LDO LDO REG 0.2A 8PIN 2.8V 1.8V 1.5V RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20 |
發(fā)布緊急采購，3分鐘左右您將得到回復。