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| 型號(hào)： | BU-66318G0-110 |
| 廠商： | DATA DEVICE CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PQFP208 |
| 封裝： | 28 X 28 MM, 1.40 MM HEIGHT, LQFP-208 |
| 文件頁(yè)數(shù)： | 31/32頁(yè) |
| 文件大?。?/td> | 278K |
| 代理商： | BU-66318G0-110 |
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8
Data Device Corporation
www.ddc-web.com
BU-66318
B-09/05-0
Signaled System Error: This bit indicates when the device has
asserted SERR#. The value after RST# is 0b.
Signaled Target Abort: This bit is set whenever the device ter-
minates a transaction with a Target-Abort. The value after RST#
is 0b.
DEVSEL# Timing: The ACE-Bridge is 01b, medium.
Fast Back-to-Back Capable: This bit is set to 1b and indicates
that the device is capable of accepting fast back-to-back trans-
actions.
Reserved: These bits are read-only and return zeroes when
read.
This data sheet describes only the PCI registers that are specif-
ic to configuring the BU-66318 for interfacing to local ACE termi-
nals, a local microprocessor, and the shared RAM. For specifics
or definitions on other PCI bus configuration registers, please
see the PCI Local Bus specification revision 2.2.
The Vendor ID field contains the vendor's ID configuration reg-
ister. Data Device Corporation's ID code is 4DDCh.
The Device ID field is used to indicate the device being used.
This field will contain a value of 0401h.
The Subsystem Vendor ID field is a programmable register that
contains the Subsystem Vendor ID information.
The Subsystem Device ID field is a programmable register that
contains the Subsystem Device ID.
The Subsystem Vendor ID and the Subsystem Device ID fields
are configured via two Subsystem ID pins (SID0 and SID1). The
use of these two signals will allow for four programming options.
TABLE 5. SUBSYSTEM VENDOR AND SUBSYSTEM
DEVICE ID SOURCE
SID 0
DESCRIPTION
0
Subsystem Vendor and Device ID's default to the
same as the System ID's
0
1
Subsystem Vendor and Device ID's are loaded by
the local processor within 225 PCI clocks after
RESET is de-asserted.
Subsystem Vendor and Device ID's are read by
the BU-66318 from an external RAM or registers.
Subsystem Vendor ID will be read from address
0000h and Subsystem Device id will be read from
address 0001h.
1
0
1
0
1
Subsystem Vendor and Device ID's are read by
the BU-66318 from an external RAM or registers.
Subsystem Vendor ID will be read from address
FFFFh and Subsystem Device id will be read from
address FFFEh.
TABLE 6. BAR0 READBACK VALUE (AFTER ALL FS
ARE WRITTEN TO BAR0)
# OF ACES
BAR0 READBACK VALUE
1
FFFE0000
2
3
FFFC0000
FFF80000
4
FFF80000
5
FFF00000
6
FFF00000
TABLE 7. (BAR0) ACE MEMORY MAP
ADDRESS OFFSET
DEFINTITION
00000 - 1FFFC
ACE 1 Memory Space
20000 - 3FFFC
40000 - 5FFFC
ACE 2 Memory Space (if available)
ACE 3 Memory Space (if available)
60000 - 7FFFC
ACE 4 Memory Space (if available)
80000 - 9FFFC
ACE 5 Memory Space (if available)
A0000 - BFFFC
ACE 6 Memory Space (if available)
Base Address Registers are used to implement ACE memory
space (BAR0), ACE register and ACE-PCI interface control reg-
ister space (BAR1), and local RAM space (BAR2). Base Address
Registers 3 through 5 are not used.
BAR0 is used to access ACE memory space. Each ACE is allot-
ted a maximum of 128K bytes (64K words) for its memory space:
The lower 4 bits being 0 indicate that BAR0 is memory space,
the address decoder is 32 bits wide and the memory is non-
prefetchable.
Not all locations may be applicable, if an ACE device is not pres-
ent (Target Abort) or the ACE does not contain 64K words. Target
aborts will result when accesses are made to:
ACE 4 when only 3 ACES are present
ACE 6 when only 5 ACES are present
Because ACE memory cannot meet PCI bus latency require-
ments directly, the BAR0 memory space is read via "delayed
read requests" and the FIFO is used for writes.
BAR1 is used to access ACE register locations (BAR1 offset
000h-5FCh) and the ACE-PCI interface control registers (offset
800h-81Ch). BAR1 will read back as FFFFF000h after all ONEs
are written to it. The lower 4 bits being 0 indicate that BAR1 is
memory space, the address decoder is 32 bits wide and the
memory is non-prefetchable.
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