- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄298893 > BXM80536GC1600F (INTEL CORP) 32-BIT, 1600 MHz, MICROPROCESSOR, CPGA478 PDF資料下載
參數(shù)資料
| 型號(hào)： | BXM80536GC1600F |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1600 MHz, MICROPROCESSOR, CPGA478 |
| 封裝： | FLIP CHIP, PGA-478 |
| 文件頁數(shù)： | 69/84頁 |
| 文件大小： | 1488K |
| 代理商： | BXM80536GC1600F |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁當(dāng)前第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁
Package Mechanical Specifications and Pin Information
Datasheet
71
BSEL[1:0]
Output
These signals are used to select the FSB clock frequency. They should be
connected between the processor and the chipset MCH and clock generator on
Intel 915 chipset family based platforms. These signals must be left
unconnected on platforms designed with the Intel 855 chipset family. On these
platforms, FSB clock frequency should be configured on the motherboard.
COMP[3:0]
Analog
COMP[3:0] must be terminated on the system board using precision (1%
tolerance) resistors. Refer to the platform design guides for more details on
implementation.
D[63:0]#
Input/
Output
D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path
between the FSB agents, and must connect the appropriate pins on both agents.
The data driver asserts DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will thus be driven four times in a
common clock period. D[63:0]# are latched off the falling edge of both
DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a
pair of one DSTBP# and one DSTBN#. The following table shows the grouping
of data signals to data strobes and DINV#.
Furthermore, the DINV# pins determine the polarity of the data signals. Each
group of 16 data signals corresponds to one DINV# signal. When the DINV#
signal is active, the corresponding data group is inverted and therefore sampled
active high.
DBR#
Output
DBR# (Data Bus Reset) is used only in processor systems where no debug port
is implemented on the system board. DBR# is used by a debug port interposer
so that an in-target probe can drive system reset. If a debug port is implemented
in the system, DBR# is a no connect in the system. DBR# is not a processor
signal.
DBSY#
Input/
Output
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on
the FSB to indicate that the data bus is in use. The data bus is released after
DBSY# is deasserted. This signal must connect the appropriate pins on both
FSB agents.
DEFER#
Input
DEFER# is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the
responsibility of the addressed memory or Input/Output agent. This signal must
connect the appropriate pins of both FSB agents.
Table 4-5. Signal Description (Sheet 2 of 7)
Name
Type
Description
Quad-Pumped Signal Groups
Data Group
DSTBN#/
DSTBP#
DINV#
D[15:0]#
0
D[31:16]#
1
D[47:32]#
2
D[63:48]#
3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BYP60K4 | 60 A, 400 V, SILICON, RECTIFIER DIODE |
| BYS10-45TR3 | 1.5 A, 45 V, SILICON, RECTIFIER DIODE |
| BYT51K | 1 A, 800 V, SILICON, SIGNAL DIODE |
| BYT51M | 1 A, 1000 V, SILICON, SIGNAL DIODE |
| BYT52A | 0.85 A, 50 V, SILICON, SIGNAL DIODE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BXM80536NC1400ES L7LS | 制造商:Intel 功能描述:CELERON M,360,1.40GHZ,1M CACHE, 400MHZ FSB,1.26V,UFCPGA - Boxed Product (Development Kits) |
| BXMP1000 | 制造商:SPECTRUM 制造商全稱:Spectrum Microwave, Inc. 功能描述:RF AMPLIFIER |
| BXMP1001 | 制造商:SPECTRUM 制造商全稱:Spectrum Microwave, Inc. 功能描述:RF AMPLIFIER |
| BXMP1002 | 制造商:SPECTRUM 制造商全稱:Spectrum Microwave, Inc. 功能描述:RF AMPLIFIER |
| BXMP1003 | 制造商:SPECTRUM 制造商全稱:Spectrum Microwave, Inc. 功能描述:RF AMPLIFIER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。