參數(shù)資料
型號(hào)： BXM80536GC1600F
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1600 MHz, MICROPROCESSOR, CPGA478
封裝： FLIP CHIP, PGA-478
文件頁(yè)數(shù)： 70/84頁(yè)
文件大?。?/td> 1488K
代理商： BXM80536GC1600F
Package Mechanical Specifications and Pin Information
72
Datasheet
DINV[3:0]#
Input/
Output
DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the
polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the
data on the data bus is inverted. The bus agent will invert the data bus signals if
more than half the bits, within the covered group, would change level in the next
cycle.
DPSLP#
Input
DPSLP# when asserted on the platform causes the processor to transition from
the Sleep State to the Deep Sleep state. In order to return to the Sleep state,
DPSLP# must be deasserted. DPSLP# is driven by the ICH4-M component and
also connects to the Intel 855 chipset family MCH-M component.
DPWR#
Input
DPWR# is a control signal from the Intel 852/855 and 915 chipset family used
to reduce power on the Intel Pentium M data bus input buffers.
DRDY#
Input/
Output
DRDY# (Data Ready) is asserted by the data driver on each data transfer,
indicating valid data on the data bus. In a multi-common clock data transfer,
DRDY# may be deasserted to insert idle clocks. This signal must connect the
appropriate pins of both FSB agents.
DSTBN[3:0]#
Input/
Output
Data strobe used to latch in D[63:0]#.
DSTBP[3:0]#
Input/
Output
Data strobe used to latch in D[63:0]#.
Table 4-5. Signal Description (Sheet 3 of 7)
Name
Type
Description
DINV[3:0]# Assignment To Data Bus
Bus Signal
Data Bus Signals
DINV[3]#
D[63:48]#
DINV[2]#
D[47:32]#
DINV[1]#
D[31:16]#
DINV[0]#
D[15:0]#
Signals
Associated Strobe
D[15:0]#, DINV[0]#
DSTBN[0]#
D[31:16]#, DINV[1]#
DSTBN[1]#
D[47:32]#, DINV[2]#
DSTBN[2]#
D[63:48]#, DINV[3]#
DSTBN[3]#
Signals
Associated Strobe
D[15:0]#, DINV[0]#
DSTBP[0]#
D[31:16]#, DINV[1]#
DSTBP[1]#
D[47:32]#, DINV[2]#
DSTBP[2]#
D[63:48]#, DINV[3]#
DSTBP[3]#
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
BXM80536NC1400ES L7LS 制造商:Intel 功能描述:CELERON M,360,1.40GHZ,1M CACHE, 400MHZ FSB,1.26V,UFCPGA - Boxed Product (Development Kits)
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