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參數(shù)資料
| 型號： | BXM80536GC1600F |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1600 MHz, MICROPROCESSOR, CPGA478 |
| 封裝： | FLIP CHIP, PGA-478 |
| 文件頁數(shù)： | 71/84頁 |
| 文件大?。?/td> | 1488K |
| 代理商： | BXM80536GC1600F |
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Package Mechanical Specifications and Pin Information
Datasheet
73
FERR#/PBE#
Output
FERR# (Floating-point Error)PBE#(Pending Break Event) is a multiplexed signal
and its meaning is qualified with STPCLK#. When STPCLK# is not asserted,
FERR#/PBE# indicates a floating point when the processor detects an
unmasked floating-point error. FERR# is similar to the ERROR# signal on the
Intel 387 coprocessor, and is included for compatibility with systems using MS-
DOS*-type floating-point error reporting. When STPCLK# is asserted, an
assertion of FERR#/PBE# indicates that the processor has a pending break
event waiting for service. The assertion of FERR#/PBE# indicates that the
processor should be returned to the Normal state. When FERR#/PBE# is
asserted, indicating a break event, it will remain asserted until STPCLK# is
deasserted. Assertion of PREQ# when STPCLK# is active will also cause an
FERR# break event.
For additional information on the pending break event functionality, including
identification of support of the feature and enable/disable information, refer to
Volume 3 of the Intel Architecture Software Developer’s Manual and the Intel
Processor Identification and CPUID Instruction
application note.
For termination requirements please refer to the platform design guides.
GTLREF
Input
GTLREF determines the signal reference level for AGTL+ input pins. GTLREF
should be set at 2/3 V
CCP. GTLREF is used by the AGTL+ receivers to determine
if a signal is a logical 0 or logical 1. Please refer to the platform design guides for
details on GTLREF implementation.
HIT#
HITM#
Input/
Output
Input/
Output
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation
results. Either FSB agent may assert both HIT# and HITM# together to indicate
that it requires a snoop stall, which can be continued by reasserting HIT# and
HITM# together.
IERR#
Output
IERR# (Internal Error) is asserted by a processor as the result of an internal
error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction
on the FSB. This transaction may optionally be converted to an external error
signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted
until the assertion of RESET#, BINIT#, or INIT#.
For termination requirements please refer to the platform design guides.
IGNNE#
Input
IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a
numeric error and continue to execute noncontrol floating-point instructions. If
IGNNE# is deasserted, the processor generates an exception on a noncontrol
floating-point instruction if a previous floating-point instruction caused an error.
IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an Input/Output write instruction, it must be valid along with the TRDY#
assertion of the corresponding Input/Output Write bus transaction.
INIT#
Input
INIT# (Initialization), when asserted, resets integer registers inside the processor
without affecting its internal caches or floating-point registers. The processor
then begins execution at the power-on Reset vector configured during power-on
configuration. The processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal. However, to ensure recognition of
this signal following an Input/Output Write instruction, it must be valid along with
the TRDY# assertion of the corresponding Input/Output Write bus transaction.
INIT# must connect the appropriate pins of both FSB agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the
processor executes its Built-in Self-Test (BIST)
For termination requirements please refer to the platform design guides.
ITP_CLK[1:0]
Input
ITP_CLK[1:0] are copies of BCLK that are used only in processor systems
where no debug port is implemented on the system board. ITP_CLK[1:0] are
used as BCLK[1:0] references for a debug port implemented on an interposer. If
a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the
system. These are not processor signals.
Table 4-5. Signal Description (Sheet 4 of 7)
Name
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BYP60K4 | 60 A, 400 V, SILICON, RECTIFIER DIODE |
| BYS10-45TR3 | 1.5 A, 45 V, SILICON, RECTIFIER DIODE |
| BYT51K | 1 A, 800 V, SILICON, SIGNAL DIODE |
| BYT51M | 1 A, 1000 V, SILICON, SIGNAL DIODE |
| BYT52A | 0.85 A, 50 V, SILICON, SIGNAL DIODE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BXM80536NC1400ES L7LS | 制造商:Intel 功能描述:CELERON M,360,1.40GHZ,1M CACHE, 400MHZ FSB,1.26V,UFCPGA - Boxed Product (Development Kits) |
| BXMP1000 | 制造商:SPECTRUM 制造商全稱:Spectrum Microwave, Inc. 功能描述:RF AMPLIFIER |
| BXMP1001 | 制造商:SPECTRUM 制造商全稱:Spectrum Microwave, Inc. 功能描述:RF AMPLIFIER |
| BXMP1002 | 制造商:SPECTRUM 制造商全稱:Spectrum Microwave, Inc. 功能描述:RF AMPLIFIER |
| BXMP1003 | 制造商:SPECTRUM 制造商全稱:Spectrum Microwave, Inc. 功能描述:RF AMPLIFIER |
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