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參數(shù)資料
| 型號： | C161CS-32R |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 16-Bit Single-Chip Microcontroller |
| 中文描述： | 16位單片機(jī) |
| 文件頁數(shù)： | 64/89頁 |
| 文件大?。?/td> | 876K |
| 代理商： | C161CS-32R |
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C161CS/JC/JI-32R
C161CS/JC/JI-L
Data Sheet
60
V3.0, 2001-01
AC Characteristics
External Clock Drive XTAL1
(Main Oscillator)
(Operating Conditions apply)
Figure 13
External Clock Drive XTAL1
Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is
limited to a range of 4 MHz to 16 MHz.
It is strongly recommended to measure the oscillation allowance (or margin) in the
final target system (layout) to determine the optimum parameters for the oscillator
operation. Please refer to the limits specified by the crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range. Operation at lower input frequencies is possible but is guaranteed by
design only (not 100% tested).
Table 11
Parameter
External Clock Drive Characteristics
Symbol
Direct Drive
1:1
Prescaler
2:1
min.
20
6
6
–
–
PLL
1:N
Unit
min.
max.
–
–
–
10
10
max.
–
–
–
6
6
min.
60
1)
10
10
–
–
max.
500
1)
–
–
10
10
Oscillator period
High time
2)
Low time
2)
Rise time
2)
Fall time
2)
t
OSCM
SR 40
t
1
t
2
t
3
t
4
1)
The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation
mode. Please see respective table above.
2)
The clock input signal must reach the defined levels
V
IL2
and
V
IH2
.
3)
The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (
f
CPU
) in
direct drive mode depends on the duty cycle of the clock input signal.
ns
ns
ns
ns
ns
SR 20
3)
SR 20
3)
SR –
SR –
MCT02534
3
t
4
t
V
IH2
V
IL
V
DD
0.5
1
t
2
t
OSC
t
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