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參數(shù)資料
| 型號： | C1851BCU |
| 廠商： | NEC Corp. |
| 英文描述： | I2C BUS-COMPATIBLE US MTS PROCESSING LSI |
| 中文描述： | I2C總線兼容美國的多邊貿(mào)易體制處理LSI |
| 文件頁數(shù)： | 15/60頁 |
| 文件大小： | 447K |
| 代理商： | C1851BCU |
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22
PC1851B
Data Sheet S13417EJ2V0DS00
3. I2C BUS INTERFACE
The
PC1851B uses a 2-wire serial bus developed by Philips. The serial clock line (SCL) and serial data line
(SDA) employ the 2-wire configuration as shown in Figure 3-1.
The
PC1851B contains an I2C bus interface circuit, eleven (8-bit) read/write registers, and one read-only register.
Serial Clock Line (SCL)
The master CPU outputs a serial clock to achieve data synchronicity. The
PC1851B receives serial data based
on this clock. The input level is CMOS-compatible. The clock frequency is from 0 to 100 kHz.
Serial Data Line (SDA)
The master CPU outputs data synchronously with the serial clock. The
PC1851B receives this data based on
the serial clock. The input level is CMOS-compatible
Figure 3-1. Internal Equivalent Circuit of Interface Pins
For SCL and SDA pins, a protection diode on the VCC side is deleted not so as to pull the voltage of I2C bus line
down to 0 V while the power supply is off (VCC = 0 V).
SCL
SDA
RP
PC1851B
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