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參數(shù)資料
| 型號： | C508 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Previous Vectron Model Numbers |
| 中文描述： | 前Vectron型號 |
| 文件頁數(shù)： | 34/93頁 |
| 文件大?。?/td> | 1204K |
| 代理商： | C508 |
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C508
Data Sheet
30
2000-08
Figure 12
Port Latch in Compare Mode 0
Compare Mode 1
In compare mode 1, the software adaptively determines the transition of the output
signal. It is commonly used when output signals are not related to a constant signal
period (as in a standard PWM Generation) but must be controlled very precisely with
high resolution and without jitter. In compare mode 1, both transitions of a signal can be
controlled. Compare outputs in this mode can be regarded as high speed outputs which
are independent of the CPU activity.
Figure 13
shows functional diagrams of the timer/compare port latch configuration in
compare mode 1. Note that the double latch structure is transparent as long as the
internal compare signal is active. While the compare signal is active, a write operation to
the port will then change both latches. This may become important when driving Timer 2
with a slow external clock. In this case the compare signal could be active for many
machine cycles in which the CPU could unintentionally change the contents of the port
latch.
A read-modify-write instruction will read the user-controlled “shadow latch” and write the
modified value back to this “shadow-latch”. A standard read instruction will - as usual -
read the pin of the corresponding compare output.
MCS04056
Port
Latch
S
D
R
CLK
Q
Q
V
DD
Port
Pin
Internal
Bus
Write to
Latch
Read Latch
Read Pin
Port Circuit
Compare Register
Circuit
Compare Reg.
Timer Circuit
Timer Register
Comparator
16-Bit
16-Bit
Compare
Match
Timer
Overflow
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