參數(shù)資料
型號: C515C-8RM
廠商: INFINEON TECHNOLOGIES AG
元件分類: DC/DC變換器
英文描述: RW-S Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 48V; Output Voltage (Vdc): 05V; Power: 2W; DIP24 Low Profile Miniature Package; 1kVDC Isolation; Feedback Regulated Output; 2:1 Wide Range Voltage Input; Continuous Short Circuit Protection; Less than 7mm Height; SMD Pinning Option; Efficiency to 87%
中文描述: 8位單片機
文件頁數(shù): 78/96頁
文件大小: 1285K
代理商: C515C-8RM
C515C
Data Sheet
74
2003-02
A/D Converter Characteristics
(Operating Conditions apply)
Parameter
Symbol
Limit Values
min.
V
AGND
Unit Test Condition
max.
V
AREF
16
×
t
IN
8
×
t
IN
96
×
t
IN
48
×
t
IN
±
2
t
ADC
/ 250
- 0.25
t
S
/ 500
- 0.25
50
Analog input voltage
Sample time
V
AIN
t
S
V
ns
1)
1)
V
AIN
may exceed
V
AGND
or
V
AREF
up to the absolute maximum ratings. However, the conversion result in
these cases will be X000
H
or X3FF
H
, respectively.
Prescaler
÷
8
Prescaler
÷
4
2)
Prescaler
÷
8
Prescaler
÷
4
3)
4)
2)
During the sample time the input capacitance
C
AIN
can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach their final voltage level within
t
S
.
After the end of the sample time
t
S
, changes of the analog input voltage have no effect on the conversion result.
Conversion cycle time
t
ADCC
ns
3)
This parameter includes the sample time
t
S
, the time for determining the digital result and the time for the
calibration. Values for the conversion clock
t
ADC
depend on programming and can be taken from the table on
the previous page.
Total unadjusted error
Internal resistance of
reference voltage source
Internal resistance of
analog source
ADC input capacitance
T
UE
R
AREF
LSB
k
4)
T
UE
is tested at
V
AREF
= 5.0 V,
V
AGND
= 0 V,
V
DD
= 4.9 V. It is guaranteed by design characterization for all
other voltages within the defined voltage range.
If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input
overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB
is permissible.
t
ADC
in [ns]
5)6)
5)
During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference source must allow the capacitance to reach their final voltage level within the
indicated time. The maximum internal resistance results from the programmed conversion timing.
6)
Not 100% tested, but guaranteed by design characterization.
R
ASRC
k
t
S
in [ns]
2)6)
C
AIN
pF
6)
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