參數(shù)資料
型號(hào): C8051F236R
廠商: Silicon Laboratories Inc
文件頁數(shù): 109/146頁
文件大小: 0K
描述: IC 8051 MCU 8K FLASH 48TQFP
標(biāo)準(zhǔn)包裝: 1
系列: C8051F2xx
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 剪切帶 (CT)
其它名稱: 336-1013-1
C8051F2xx
Rev. 1.6
65
9.2.
Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. There are 256 bytes of internal data
memory and 8 kB of internal program memory address space implemented within the CIP-51. The CIP-51
memory organization is shown in Figure 9.2.
9.2.1. Program Memory
The CIP-51 has a 8 kB program memory space. The MCU implements 8320 bytes of this program mem-
ory space as in-system, reprogrammable Flash memory, organized in a contiguous block from addresses
0x0000 to 0x207F. Note: 512 bytes (0x1E00 – 0x1FFF) of this memory are reserved for factory use and
are not available for user program storage.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature pro-
vides a mechanism for the CIP-51 to update program code and use the program memory space for non-
volatile data storage. Refer to Section 10 Flash Memory for further details.
9.2.2. Data Memory
The CIP-51 implements 256 bytes of internal RAM mapped into the data memory space from 0x00 through
0xFF. The lower 128 bytes of data memory are used for general purpose registers and memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or
as 128 bit locations accessible with the direct bit addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space.
Instructions using indirect addressing above 0x7F will
access the upper 128 bytes of data memory. Figure 9.2 illustrates the data memory organization of the
CIP-51.
Additionally, the C8051F206/226/236 feature 1024 Bytes of RAM mapped in the external data memory
space. All address locations may be accessed using the MOVX instruction. (Please see Section 11).
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