參數(shù)資料
型號(hào)： C8051F236R
廠商： Silicon Laboratories Inc
文件頁數(shù)： 14/146頁
文件大?。?/td> 0K
描述： IC 8051 MCU 8K FLASH 48TQFP
標(biāo)準(zhǔn)包裝： 1
系列： C8051F2xx
核心處理器： 8051
芯體尺寸： 8-位
速度： 25MHz
連通性： SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 48-TQFP
包裝： 剪切帶 (CT)
其它名稱： 336-1013-1
C8051F2xx
110
Rev. 1.6
15. Serial Peripheral Interface Bus
The Serial Peripheral Interface (SPI) provides access to a four-wire, full-duplex, serial bus. SPI supports
the connection of multiple slave devices to a master device on the same bus. A separate slave-select sig-
nal (NSS) is used to select a slave device and enable a data transfer between the master and the selected
slave. Multiple masters on the same bus are also supported. Collision detection is provided when two or
more masters attempt a data transfer at the same time. The SPI can operate as either a master or a slave.
When the SPI is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system
clock frequency.
When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation
is 1/10 the system clock frequency, provided that the master issues SCK, NSS, and the serial input data
synchronously with the system clock. If the master issues SCK, NSS, and the serial input data asynchro-
nously, the maximum data transfer rate (bits/sec) must be less that 1/10 the system clock frequency. In the
special case where the master only wants to transmit data to the slave and does not need to receive data
from the slave (i.e. half-duplex operation), the SPI slave can receive data at a maximum data transfer rate
(bits/sec) of the system clock frequency. This is provided that the master issues SCK, NSS, and the
serial input data synchronously with the system clock.
Figure 15.1. SPI Block Diagram
SFR Bus
Clock Divide
Logic
Data Path
Control
SFR Bus
Write to
SPI0DAT
Receive Data Register
SPI0DAT
0
1
2
3
4
5
6
7
Shift Register
SPI CONTROL LOGIC
Bit Count
Logic
SPI0CKR
S
C
R
7
S
C
R
6
S
C
R
5
S
C
R
4
S
C
R
3
S
C
R
2
S
C
R
1
S
C
R
0
SPI0CFG
C
K
P
H
A
C
K
P
O
L
B
C
2
B
C
1
B
C
0
F
R
S
2
F
R
S
1
F
R
S
0
SPI0CN
M
O
D
F
T
X
B
S
Y
S
L
V
S
E
L
M
S
T
E
N
S
P
I
E
N
W
C
O
L
S
P
I
F
R
X
O
V
R
N
Pin Control
Interface
SPI Clock
(Master Mode)
Pin
Control
Logic
P
O
R
T
2
M
U
X
Read
SPI0DAT
SPI IRQ
SYSCLK
Tx Data
Rx Data
SCK
MISO
MOSI
NSS
P2.0 SCK
P2.1 MISO
P2.2 MOSI
P2.3 NSS
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