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參數(shù)資料
| 型號： | C8051T606TDB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 28/188頁 |
| 文件大?。?/td> | 0K |
| 描述： | CARD DAUGHTER MSOP SOCKET |
| 標準包裝： | 1 |
| 模塊/板類型： | MSOP 插口模塊 |
| 適用于相關(guān)產(chǎn)品： | C8051T606 |
| 產(chǎn)品目錄頁面： | 626 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | 336-1663-6-ND - IC 8051 MCU 1.5K-EEPROM 10-QFN 336-1663-2-ND - IC 8051 MCU 1.5K-EEPROM 10-QFN 336-1664-5-ND - IC 8051 MCU 1.5K-EEPROM 10-MSOP 336-1663-1-ND - IC 8051 MCU 1.5K-EEPROM 10-QFN 336-1662-5-ND - IC 8051 MCU 1.5K-EEPROM 11-QFN |
| 其它名稱： | 336-1667 |
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Rev. 1.2
123
C8051T600/1/2/3/4/5/6
When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to
reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to
overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable
and re-enable) the SMBus in the event of an SCL low timeout.
23.3.5. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more than 50 s, the bus
is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and
SDA remain high for more than 10 SMBus clock source periods (as defined by the timer configured for the
SMBus clock source). If the SMBus is waiting to generate a Master START, the START will be generated
following this timeout. A clock source is required for free timeout detection, even in a slave-only implemen-
tation.
23.4. Using the SMBus
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con-
trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides
the following application-independent features:
Byte-wise serial data transfers
Clock signal generation on SCL (Master Mode only) and SDA data synchronization
Timeout/bus error recognition, as defined by the SMB0CF configuration register
START/STOP timing, detection, and generation
Bus arbitration
Interrupt generation
Status information
SMBus interrupts are generated for each data byte or slave address that is transferred. When a transmitter
(i.e., sending address/data, receiving an ACK), this interrupt is generated after the ACK cycle so that soft-
ware may read the received ACK value; when receiving data (i.e., receiving address/data, sending an
ACK), this interrupt is generated before the ACK cycle so that software may define the outgoing ACK
value. See Section 23.5 for more details on transmission sequences.
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated) or
the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control
register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section 23.4.2;
Table 23.4 provides a quick SMB0CN decoding reference.
23.4.1. SMBus Configuration Register
The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes,
select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is
set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the
INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,
the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit
is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of
the current transfer).
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| C8051T606ZDB | 功能描述:子卡和OEM板 QFN10 (2x2mm) Socket Daughter Card RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| C8051T606-ZM | 功能描述:8位微控制器 -MCU 1.5K OTP EPROM MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| C8051T606-ZMR | 功能描述:8位微控制器 -MCU 1.5K OTP EPROM MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| C8051T610DB24 | 功能描述:仿真器/模擬器 C8051T610 Family Socket Daughtr Board RoHS:否 制造商:Blackhawk 產(chǎn)品:System Trace Emulators 工具用于評估:C6000, C5000, C2000, OMAP, DAVINCI, SITARA, TMS470, TMS570, ARM 7/9, ARM Cortex A8/R4/M3 用于:XDS560v2 |
| C8051T610DB28 | 功能描述:子卡和OEM板 C8051T610 Family Socket Daughtr Board RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
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