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參數(shù)資料
| 型號(hào)： | C9821GQ |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | 單時(shí)鐘驅(qū)動(dòng)器| SSOP封裝| 24針|塑料 |
| 文件頁(yè)數(shù)： | 3/18頁(yè) |
| 文件大?。?/td> | 121K |
| 代理商： | C9821GQ |
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Direct Rambus
Plus Clock Generator
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07092 Rev. **
05/03/2001
Page 3 of 18
APPROVED PRODUCT
C9821
System Clock Configuration
Figure 3 shows the clocking configuration for an example Direct Rambus subsystem. The configuration shows the
interconnection of the system clock source, the C9821, and the clock signals of a memory controller ASIC. The ASIC
contains the RAC, the Rambus Memory Controller protocol engine (RMC), and logic to support synchronizing the
Channel clock with the controller clock (This diagram represents the differential clocks as a single Busclk wire).
M N
C9801
C9812
C9830
C9840
C9850
C9851
C9853
PLL
Phase
Align
D
C9821
DLL
4
RMC
Pclk
Refclk
S0/S1/S2 STOPB
Busclk
RAC
Synclk
Gear
Ratio
Logic
S
P
Figure: 3 DDLL System Architecture
This configuration achieves frequency-lock between the controller and Rambus Channel clocks (Pclk and Synclk).
these clock signals are matched and phase-aligned at the RMC/RAC boundary in order to allow data transfers to
occur across this boundary without additional latency.
The main clock source drives the system clock (Pclk) to the ASIC, and also drives the reference clock (Refclk) to the
C9821. Refclk is not the same frequency as Pclk. A PLL inside the C9821 multiplies Refclk to generate the desired
frequency for Busclk. Busclk is driven on the Rambus Channel through a terminated transmission line. At the mid-
point of the Channel, the RAC senses Busclk using its own DLL for clock alignment, followed by a fixed divide-by-4
circuit that generates SynClk.
Pclk is the clock used in the Rambus memory controller (RMC) in the ASIC. SynClk is the clock used at the ASIC
interface of the RAC. The C9821 together with the Gear Ratio Logic enables the controller to exchange data directly
from the Pclk domain to the SynClk domain without incurring additional latency for synchronization. In general, Pclk
and SynClk can run at different frequencies, so the Gear Ratio Logic must select the appropriate M and N dividers
such that the frequencies of Pclk/M and SynClkN are equal. In one example, Pclk = 133 MHz and SynClk = 100
MHz, and M = 4 while N = 3, giving Pclk/M = SynClk/N = 33 MHz.
The ASIC drives the output clocks, Pclk and SynClk/N from the Gear Ratio Logic to the C9821 Phase Detector
inputs. The routing of the Pclk/M and SynClk/N signal traces must be matched in impedance and propagation delay
on the ASIC as well as on the board. These signals are not part of the Rambus Channel and board designers must
match their routing.
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