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參數(shù)資料
| 型號： | C9821GQ |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | 單時鐘驅(qū)動器| SSOP封裝| 24針|塑料 |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 121K |
| 代理商： | C9821GQ |
Direct Rambus
Plus Clock Generator
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07092 Rev. **
05/03/2001
Page 7 of 18
APPROVED PRODUCT
C9821
Power Management Functions (Cont.)
The device is able to turn off the Rambus Channel clock to minimize power for mobile and other power-sensitive
applications. In the “clock off” mode, the device remains on while the output is disabled, allowing fast transitions
between the clock-off and clock-on states. This mode could be used in conjunction with the Nap mode of the
RDRAMs and Rambus ASIC Cell (RAC). When output clocks are in a power down mode they are driven to and held
at a logic low level by the device.
In the “power down” mode, the device is completely powered down for minimum power dissipation. This mode is
used in conjunction with the power down modes of the RDRAMs and RAC.
The device has three operating states: Normal, Clock off and Powerdown. In normal mode, the clock source is on,
and the output is enabled. In Clock off mode, the clock source is on, but the output is disabled (StopB asserted). In
powerdown mode, the device is powered down with the control signal PwrDnB equal to 0. The control signals Mult0,
Mult1, S0, S1, and S2 must be stable before power is applied to the device, and can only be changed in power-down
mode (PwrDnB=0).
Power Management Modes
State
PwrDnB
1
1
0
StopB
1
0
X
Normal
Clock Off
Powerdown
Table 6: Control Signals for Clock Source States
Upon applying power to the device, the device can enter any state, depending on the settings of the control signals,
PwrDnB and StopB. the clock source output need not be glitch-free during state transitions.
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