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參數(shù)資料
| 型號(hào)： | CA16 |
| 英文描述： | CA16-Type 2.5 Gbits/s DWDM Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer |
| 中文描述： | CA16型2.5 Gb /秒的DWDM轉(zhuǎn)發(fā)器，16通道155 Mbits /秒復(fù)用器/解復(fù)用器 |
| 文件頁數(shù)： | 11/30頁 |
| 文件大?。?/td> | 464K |
| 代理商： | CA16 |
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11
Agere Systems Inc.
Advance Data Sheet
March 2001
CA16-Type 2.5 Gbits/s DWDM Transponder with
16-Channel 155 Mbits/s Multiplexer/Demultiplexer
Pin Descriptions
(continued)
* Future versions of the cooled transponder will not support the frame-detect function.
Table 3. CA16-Type Transponder Output Pin Descriptions
Pin Name
Pin Description
RxQ[0:15]P
RxQ[0:15]N
16-Bit Differential LVPECL Parallel Output Data Bus
. RxQ[0:15] is the 155 Mbyte/s 16-bit output
word. RxQ15P/N is the most significant bit of the received word and is the first bit serialized.
RxQ00P/N is the least significant bit of the received word and is the last bit serialized. RxQ[0:15]P/
N is updated on the falling edge of POC
LK
.
Differential LVPECL Parallel Output Clock
. A 155 MHz nominally 50% duty cycle, byte rate out-
put clock that is aligned to the RxQ[0:15] byte serial output data. RxQ[0:15] and FP are updated on
the falling edge of POC
LK
.
Frame Pulse (LVPECL).
Indicates frame boundaries in the received serial data stream. If framing
pattern detection is enabled (FRAMEN high and OOF), FP pulses high for one POC
LK
cycle when
a 32-bit sequence matching the framing pattern is detected in the received serial data. FP is
updated on the falling edge of POC
LK
.
A1 A2 Frame Search Output (LVTTL)
. A high on this output pin indicates that the frame detection
circuit is active and is searching for a new A1 A2 byte alignment. This output will be high during the
entire A1 A2 frame search. Once a new alignment is found, this signal will remain high for a mini-
mum of one 155 MHz clock period beyond the third A2 byte before it will be set low.
Loss of Signal (LVTTL)
. A low on this output indicates a loss of clock by the clock recovery circuit
in the optical receiver.
Laser Bias Alarm (Analog)
. The analog bias alarm is not available on the CA16 transponders.
Laser Degrade Alarm (5 V CMOS).
This output goes to a logic 0 when the laser output power
degrades 2 dB below the nominal output power.
Laser Power Monitor (Analog)
. Provides an indication of the output power level from the transmit-
ter laser. This output is set at 500 mV for the nominal transmitter optical output power. If the optical
power decreases by 3 dB, this output will drop to approximately 250 mV, and if the output power
should increase by 3 dB, this output will increase to 1000 mV.
Parallel Byte Clock (Differential LVPECL)
. A byte-rate reference clock generated by dividing the
internal 2.488 GHz serial bit clock by 16. This output is normally used to synchronize byte-wide
transfers from upstream logic into the CA16 transponder. See timing discussion for additional
details, page 18.
Phase Error Signal (Single-Ended LVPECL)
. Pulses high during each PC
LK
cycle for which there
is a potential setup/hold timing violation between the internal byte clock and the PIC
LK
timing
domain. PHERR is updated on the falling edge of the PC
LK
outputs.
Receiver Photodiode Current Monitor (Analog).
This output provides a current output that is a
mirror of the of the photocurrent generated by the optical receiver’s photodetector diode (APD or
PIN). A 10 k
resistor from pin 2 to ground provides a voltage at this output ranging from ~1 mV to
~800 mV, depending on the optical input power.
Wavelength Deviation Alarm (5 V TTL).
This output changes logic levels whenever the optical
transmitter’s wavelength deviates from the nominal wavelength by more than ±100
pm.
Lock Detect (LVTTL).
This output goes low after the transmit side PLL has locked to the clock sig-
nal provided at the T
X
R
EF
C
LK
input pins. LOCKDET is an asychronous output.
POC
LK
P
POC
LK
N
FP
*
SEARCH
*
LOS
LSRBIAS
LSRALM
LPM
PC
LK
P/N
PHERR
IPDMON
WDEA
LOCKDET
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