參數(shù)資料
型號(hào)： CA16
英文描述： CA16-Type 2.5 Gbits/s DWDM Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer
中文描述： CA16型2.5 Gb /秒的DWDM轉(zhuǎn)發(fā)器，16通道155 Mbits /秒復(fù)用器/解復(fù)用器
文件頁數(shù)： 19/30頁
文件大?。?/td> 464K
代理商： CA16
19
Agere Systems Inc.
Advance Data Sheet
March 2001
CA16-Type 2.5 Gbits/s DWDM Transponder with
16-Channel 155 Mbits/s Multiplexer/Demultiplexer
Timing Characteristics
(continued)
Input Timing Mode 1
In the configuration shown in Figure 5, PHERR to
PHINIT has a zero delay (shorted on the PCB) and the
PC
LK
is used to clock 16-bit-wide data out of the cus-
tomer ASIC. The FIFO in the multiplexer ia 16-bits wide
and six registers deep.
The PC
LK
and PIC
LK
signals respectively control the
READ and WRITE counters for the FIFO. The data
bank from the FIFO has to be read by the internally
generated clock (PC
LK
) only once after it has been writ-
ten by the PIC
LK
input.
Since the delay in the customer ASIC is unknown, the
two clocks (PC
LK
and PIC
LK
) might drift in respect to
each other and try to perform the read and writer oper-
ation on the same bank in the FIFO at the same time.
However, before such a clock mismatch can occur,
PHERR goes high and, if externally connected to
PHINIT, will initialize the FIFO provided PHINIT
remains high for at least two byte clocks. One to three
16-bit words of data will be lost during the initialization
of the FIFO.
Figure 5. Block Diagram Timing Mode 1
CUSTOMER LOGIC
CA16 TRANSPONDER
FIFO
PLL
DIVIDER
OSCILLATOR
155.52 MHz
±
20 ppm
T
X
REFCLK
16
PHERR
PHINIT
PCLK
PICLK
LOCKDET
TIMING
GENERATOR
INTERNAL
PCLK
TXD[0:15]
CLOCK
DATA
CENTERS
FIFO
D
Q
1-1121(F).b
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CA16A2Cnn CA16-Type 2.5 Gbits/s DWDM Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer
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