參數(shù)資料
型號： CA16
英文描述： CA16-Type 2.5 Gbits/s DWDM Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer
中文描述： CA16型2.5 Gb /秒的DWDM轉(zhuǎn)發(fā)器，16通道155 Mbits /秒復(fù)用器/解復(fù)用器
文件頁數(shù)： 20/30頁
文件大?。?/td> 464K
代理商： CA16
20
Agere Systems Inc.
CA16-Type 2.5 Gbits/s DWDM Transponder with
16-Channel 155 Mbits/s Multiplexer/Demultiplexer
Advance Data Sheet
March 2001
Transmitter Data Input Timing
(continued)
Input Timing Mode 2
To avoid the loss of data, idle or dummy bytes should
be sent on the T
X
D[0:15] bus whenever PHERR goes
high. In the configuration shown in Figure 6, the
PHERR signal is used as an input to the customer
logic. Upon detecting a high on the PHERR signal, the
customer logic should return a high signal, one that
remains high for at least two byte-clock cycles, to the
PHINIT input of the CA16. Also, when PHERR goes
high, the customer logic should start sending idle or
dummy bytes to the CA16 on the T
X
D[0:15] bus. This
should continue until PHERR goes low.
The FIFO is initialized two-to-eight byte clocks after
PHINIT goes high for two byte clocks. PHERR goes low
after the FIFO is initialized. Upon detecting a low on
PHERR, the customer logic can start sending real data
bytes on T
X
D[0:15]. The two timing loops (PC
LK
to
PIC
LK
and PHERR to PHINIT) do not have to be of
equal length.
Figure 6. Block Diagram Timing Mode 2
CUSTOMER LOGIC
CA16 TRANSPONDER
FIFO
PLL
DIVIDER
OSCILLATOR
155.52 MHz
±
20 ppm
T
X
REFCLK
16
PHERR
PHINIT
PCLK
PICLK
LOCKDET
TIMING
GENERATOR
INTERNAL
PCLK
TXD[0:15]
CLOCK
DATA
CENTERS
FIFO
D
Q
1121(F).b
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