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參數(shù)資料
| 型號： | CA95C09-10CN |
| 元件分類： | 加密電路 |
| 英文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 22/42頁 |
| 文件大?。?/td> | 180K |
| 代理商： | CA95C09-10CN |
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Tundra Semiconductor Corporation
CA95C68/18/09
Tundra Semiconductor Corporation
3-53
PROGRAMMING INSTRUCTIONS FOR MULTIPLEXED CONTROL MODE
4)
One of the three Start commands is then written to the
Command Register to begin the ciphering session.
5)
Once a Start command is entered, the DCP will indicate
that it is ready for data input by activating the
corresponding ag bit in the Status Register, as well as
the associated input ag pin. Data can now be input
through the assigned Input Port. The two ags,
and
, which are associated with the Data Registers
can be sensed by hardware or software to know when
data is to be entered or removed from the DCP.
6)
As soon as the Input ag is active, the DCP is ready to
accept data (MSB rst). This bit is deactivated once eight
bytes of data have been entered.
7)
The Output ag goes active whenever the DES algorithm
is completed and data is ready to be removed from the
Output Register.
8)
Data is removed from the Output Port one byte at a time
with the most signicant byte rst. The Output ag
becomes inactive upon the removal of the eighth byte.
9)
Loop through steps 5 through 9 until the ciphering
session should be terminated.
10) The session can now be terminated by issuing the Stop
command to the Command Register.
Upon termination, all remaining processed data is available in
the Output Register until the DCP is reset. This allows you to
enter the Stop command immediately upon entering the last
input block. When all the data has been removed from the
Output Register, all the ags will be inactive. If the DCP is
restarted, any data that was not read out from the previous
ciphering session will be lost.
MFLG
SFLG
This section describes the registers that need programming
prior to using the DCP in ECB, CBC, or CFB ciphering
modes in Multiplexed Control Mode (MCM) of operation.
The
programming
ow
charts
for
each
mode
are
implemented for a single 8 bit port interface (see the
pipelining section for the dual port programming ow chart).
ECB Operation
Figure 3-18 illustrates the programming sequence for ECB.
1)
A hardware or software reset must be implemented to
bring the device to a known state. A reset clears all bits
in the Status Register and programs the Mode Register
to it's default setting.
2)
Program the Mode Register (see Figure 3-16) with the
cipher type and the port conguration. For further
explanation see the Mode Register description.
3)
The clear Encryption or Decryption Keys can be loaded
through either the Master or Auxiliary Ports. The
Command Pending bit in the Status Register will go
active once a command has been entered in the
Command Register. This bit will be active until all eight
bytes of the key have been loaded into the Input
Register of the DCP.
An alternative method to Step 3 is to load a Master Key
into the DCP through the Auxiliary Port. When this
command is entered the AFLG bit in the Status Register
will go active (
output pin will be active low) until
all 8 bytes have been entered. One key byte is loaded on
each rising edge of the Auxiliary Strobe (
).
A Load Encrypted Session Key command is then
entered into the DCP. The Session Key is then decrypted
by the Master Key before being stored in the
corresponding register. This use of the Master Key
allows you to enhance security by frequently changing
the session keys over a communication link.
AFLG
ASTB
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