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參數(shù)資料
| 型號： | CA95C09-10CN |
| 元件分類： | 加密電路 |
| 英文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 7/42頁 |
| 文件大?。?/td> | 180K |
| 代理商： | CA95C09-10CN |
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Tundra Semiconductor Corporation
CA95C68/18/09
Tundra Semiconductor Corporation
3-39
Table 3-3b (con’t): AC Characteristics (TA = 0 to 70°C, VDD = +5.0V ± 5%, VSS = 0V)
Notes:
1)
All input transition times assumed <5ns, except clock which is <3ns (for 25 and 33MHz timing).
2)
The appropriate input ag (
,
) goes active LOW after 1 CLK
↓ +30ns from the writing of a “Load” or
“Start” command.
3)
When S/S goes inactive (LOW) in Direct Control Mode, the ag associated with the Input Port will turn off.
4)
Direct Control Mode only (
must be LOW for one falling edge during a read/write cycle).
5)
In Cipher Feedback, the Port Flag (
or
) will go inactive following the leading edge of the rst data strobe
(
,
, or
), in all other modes and operations, the ags go inactive on the eighth data strobe.
6)
Do not change K/D until
is inactive (HIGH).
7)
Do not change E/D until
(
) is inactive (HIGH).
8)
In Cipher Feedback,
must be inactive (HIGH) before S/S goes inactive (LOW).
9)
must go active (LOW) before
goes active (LOW).
10) tWL is the clock width LOW (number t2).
11) tC is the clock cycle time (number t3).
12) All output timing specications reect the following: High output >1.5V, Low output <1.5V.
13) All output timings assume CLOAD = 50pF.
14) When operating in Direct Control Mode, you must ensure that the K/D input is valid one clock cycle before you begin to load
the key, or perform any data operations with the device.
15) Timing numbers for parameter t49 with CLOAD = 25 pF are shown below for a 33 MHz device:
For CA95C68:
LOW to Read Data VALID (Read Access Time): 23.5 ns
For CA95C18:
LOW to Read Data VALID (Read Access Time): 23.5 ns
For CA95C68/18:
LOW to Read Data VALID (Read Access Time): 19 ns
16) These input signals must be externally synchronized to the CA95C09’s clock. As a result, there is less timing margin as the
frequency increases (ie: @ 33 MHz). Designers should review these timing parameters early on in the design cycle to ensure
that their interface logic to the CA95C09/18/68 will be able to meet these timing requirements.
Number
5 MHz Limits
10 MHz Limits
16 MHz Limits
20 MHz Limits
25 MHz Limits
33 MHz Limits
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Auxiliary Port Key Entry
t61
80
–
40
–
30
–
20
–
20
–
15
–
ns
t62
5tC-20
5
tC-20
5
tC-20
5
tC-20
5
tC-20
-12
tC-20
ns
t63
30
–
20
–
15
–
10
–
10
–
8
–
ns
t64
40
–20
–
15
–10
–5–3–ns
t65
20
–20
–
15
–15
–5–3–ns
t66
–
75
–
50
–
40
–
35
–
30
–
25
ns
t67
–
75
–
50
–
40
–
35
–
30
–
20
ns
MFLG
SFLG
AFLG
MCS
MFLG
SFLG
MRD
MWR
MDS
SDS
CP
MFLG
SFLG
BSY
AFLG
ASTB
MRD
MDS
SDS
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