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參數(shù)資料
| 型號： | CAP1028-1-BP-TR |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, QCC20 |
| 封裝： | 4 X 4 MM, ROHS COMPLAINT, QFN-20 |
| 文件頁數(shù)： | 7/69頁 |
| 文件大?。?/td> | 948K |
| 代理商： | CAP1028-1-BP-TR |
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8 Channel Capacitive Touch Sensor with 2 LED Drivers
Datasheet
SMSC CAP1028
15
Revision 1.0 (06-16-09)
DATASHEET
3.2
System Management Bus
The CAP1028 communicates with a host controller, such as an SMSC SIO, through the SMBus. The
SMBus is a two-wire serial communication protocol between a computer host and its peripheral
devices. A detailed timing diagram is shown in Figure 3.1. Stretching of the SMCLK signal is supported;
however, the CAP1028 will not stretch the clock signal.
3.2.1
SMBus Start Bit
The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic
‘0’ state while the SMBus Clock line is in a logic ‘1’ state.
3.2.2
SMBus Address and RD / WR Bit
The SMBus Address Byte consists of the 7-bit client address followed by the RD / WR indicator bit. If
this RD / WR bit is a logic ‘0’, then the SMBus Host is writing data to the client device. If this RD / WR
bit is a logic ‘1’, then the SMBus Host is reading data from the client device.
See Table 3.1 for available SMBus addresses.
3.2.3
SMBus Data Bytes
All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.
3.2.4
SMBus ACK and NACK Bits
The SMBus client will acknowledge all data bytes that it receives. This is done by the client device
pulling the SMBus Data line low after the 8th bit of each byte that is transmitted. This applies to both
the Write Byte and Block Write protocols.
The Host will NACK (not acknowledge) the last data byte to be received from the client by holding the
SMBus data line high after the 8th data bit has been sent. For the Block Read protocol, the Host will
ACK each data byte that it receives except the last data byte.
3.2.5
SMBus Stop Bit
The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic
‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the CAP1028 detects an SMBus Stop
bit, and it has been communicating with the SMBus protocol, it will reset its client interface and prepare
to receive further communications.
Figure 3.1 SMBus Timing Diagram
SMDATA
SMCLK
TLOW
TRISE
THIGH
TFALL
TBUF
THD:STA
P
S
S - Start Condition
P - Stop Condition
THD:DAT
TSU:DAT
TSU:STA
THD:STA
P
TSU:STO
S
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