參數(shù)資料
型號: CAT28F102NA-12T
元件分類: PROM
英文描述: 64K X 16 FLASH 12V PROM, 120 ns, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 1/15頁
文件大?。?/td> 107K
代理商: CAT28F102NA-12T
1
FEATURES
s Fast Read Access Time: 100/120 ns
s Low Power CMOS Dissipation:
–Active: 30 mA max (CMOS/TTL levels)
–Standby: 1 mA max (TTL levels)
–Standby: 100
A max (CMOS levels)
s High Speed Programming:
–10
s per byte
–1 Sec Typ Chip Program
s 0.5 Seconds Typical Chip-Erase
s 12.0V
± 5% Programming and Erase Voltage
s Commercial,Industrial and Automotive
Temperature Ranges
s 64K x 16 Word Organization
s Stop Timer for Program/Erase
s On-Chip Address and Data Latches
s JEDEC Standard Pinouts:
–40-pin DIP
–44-pin PLCC
–40-pin TSOP
s 100,000 Program/Erase Cycles
s 10 Year Data Retention
s Electronic Signature
CAT28F102
1 Megabit CMOS Flash Memory
DESCRIPTION
The CAT28F102 is a high speed 64K x 16-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard
EPROM and E2PROM devices. Programming and Erase
are performed through an operation and verify algorithm.
The instructions are input via the I/O bus, using a two
write cycle scheme. Address and Data are latched to
free the I/O bus and address bus during the write
operation.
The CAT28F102 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 40-pin DIP, 44-pin PLCC, or 40-pin TSOP
packages.
BLOCK DIAGRAM
Licensed Intel
second source
2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
I/O0–I/O15
I/O BUFFERS
CE, OE LOGIC
SENSE
AMP
DATA
LATCH
ERASE VOLTAGE
SWITCH
PROGRAM VOLTAGE
SWITCH
COMMAND
REGISTER
CE
OE
WE
VOLTAGE VERIFY
SWITCH
ADDRESS
LA
TCH
Y-DECODER
X-DECODER
Y-GATING
1,048,576-BIT
MEMORY
ARRAY
A0–A15
Doc. No. 1014, Rev. A
Main Menu
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