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參數(shù)資料
| 型號： | CAT28F102NA-12T |
| 元件分類： | PROM |
| 英文描述： | 64K X 16 FLASH 12V PROM, 120 ns, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 15/15頁 |
| 文件大?。?/td> | 107K |
| 代理商： | CAT28F102NA-12T |
CAT28F102
9
Doc. No. 1014, Rev. A
WRITE OPERATIONS
The following operations are initiated by observing the
sequence specified in the Write Command Table.
Read Mode
The device can be put into a standard READ mode by
initiating a write cycle with XX00H on the data bus. The
subsequent read cycles will be performed similar to a
standard EPROM or E2PROM Read.
Signature Mode
An alternative method for reading device signature (see
Read Operations Signature Mode), is initiated by writing
the code XX90H into the command register while keeping
VPP high. A read cycle from address 0000H with
CE and
OE low (and WE high) will output the device signature.
CATALYST Code = 0000 0000 0011 0001 (0031H)
A Read cycle from address 0001H retrieves the binary
code for the device on outputs I/O0 to I/O7.
28F102 Code = 0000 0000 0101 0001 (0051H)
Figure 6. A.C. Timing for Erase Operation
Erase-Verify Mode
The Erase-verify operation is performed on every byte
after each erase pulse to verify that the bits have been
erased.
Erase Mode
During the first Write cycle, the command XX20H is
written into the command register. In order to commence
the erase operation, the identical command of XX20H
has to be written again into the register. This two-step
process ensures against accidental erasure of the
memory contents. The final erase cycle will be stopped
at the rising edge of
WE, at which time the Erase Verify
command (XXA0H) is sent to the command register.
During this cycle, the address to be verified is sent to the
address bus and latched when
WE goes low. An
integrated stop timer allows for automatic timing control
over this operation, eliminating the need for a maximum
erase timing specification. Refer to AC Characteristics
(Program/Erase) for specific timing parameters.
ADDRESSES
28F102 F06
CE (E)
OE (G)
WE (W)
DATA (I/O)
VCC
VPP
tWC
tRC
tCS
tCH
tCS
tCH
tEHQZ
tDF
tGHWL
tWPH
tWHWH2
tWHGL
tWP
tDS
HIGH-Z
DATA IN
= XX20H
DATA IN
= XXA0H
VALID
DATA OUT
tDH
tWP
tDH
tDS
tWP
tDH
tOLZ
tOE
tOH
tLZ
tCE
tVPEL
VPPH
VPPL
0V
5.0V
VCC POWER-UP
& STANDBY
SETUP ERASE
COMMAND
ERASE
COMMAND
ERASING
ERASE VERIFY
COMMAND
ERASE
VERIFICATION
VCC POWER-DOWN/
STANDBY
tAS
tAH
DATA IN
= XX20H
tWC
Main Menu
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