Table 6. PIN CAPACITANCE (Note 8) (TA
參數(shù)資料
型號(hào): CAT5261YI-00-T2
廠商: ON Semiconductor
文件頁數(shù): 11/14頁
文件大小: 0K
描述: IC POT DIG 100K 256T SPI 24TSSOP
標(biāo)準(zhǔn)包裝: 2,000
系列: DPP
接片: 256
電阻(歐姆): 100k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 300 ppm/°C
存儲(chǔ)器類型: 非易失
接口: 6 線 SPI(芯片選擇,設(shè)備位址)
電源電壓: 2.5 V ~ 6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
CAT5261
http://onsemi.com
6
Table 6. PIN CAPACITANCE (Note 8) (TA = 25C, f = 1.0 MHz, VCC = 5 V, unless otherwise specified.)
Symbol
Test
Conditions
Max
Units
COUT (Note 8)
Output Capacitance (SO)
VOUT = 0 V
8
pF
CIN (Note 8)
Input Capacitance (CS, SCK, SI, WP, HOLD, A0, A1)
VIN = 0 V
6
pF
Table 7. A.C. CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
Max
Units
tSU
Data Setup Time
CL = 50 pF
50
ns
tH
Data Hold Time
50
ns
tWH
SCK High Time
125
ns
tWL
SCK Low Time
125
ns
fSCK
Clock Frequency
DC
3
MHz
tLZ
HOLD to Output Low Z
50
ns
tRI (Note 8)
Input Rise Time
2
ms
tFI (Note 8)
Input Fall Time
2
ms
tHD
HOLD Setup Time
100
ns
tCD
HOLD Hold Time
100
ns
tV
Output Valid from Clock Low
200
ns
tHO
Output Hold Time
0
ns
tDIS
Output Disable Time
250
ns
tHZ
HOLD to Output High Z
100
ns
tCS
CS High Time
2
ns
tCSS
CS Setup Time
250
ns
tCSH
CS Hold Time
250
ns
8. This parameter is tested initially and after a design or process change that affects the parameter.
Table 8. POWER UP TIMING (Notes 9, 10)
Symbol
Parameter
Max
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
Table 9. WIPER TIMING
Symbol
Parameter
Min
Max
Units
tWRPO
Wiper Response Time After Power Supply Stable
5
10
ms
tWRL
Wiper Response Time After Instruction Issued
5
10
ms
Table 10. WRITE CYCLE LIMITS
Symbol
Parameter
Max
Units
tWR
Write Cycle Time
5
ms
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