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參數(shù)資料
| 型號： | CAT5261YI-00-T2 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 13/14頁 |
| 文件大小： | 0K |
| 描述： | IC POT DIG 100K 256T SPI 24TSSOP |
| 標準包裝： | 2,000 |
| 系列： | DPP |
| 接片： | 256 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 6 線 SPI（芯片選擇，設備位址） |
| 電源電壓： | 2.5 V ~ 6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
CAT5261
http://onsemi.com
8
INSTRUCTION AND REGISTER DESCRIPTION
Device Type/Address Byte
The first byte sent to the CAT5261 from the master/
processor is called the Device Address Byte. The most
significant four bits of the Device Type address are a device
type identifier. These bits for the CAT5261 are fixed at
0101[B] (refer to Figure 4).
The two least significant bits in the slave address byte, A1
A0, are the internal slave address and must match the
physical device address which is defined by the state of the
A1 A0 input pins for the CAT5261 to successfully continue
the command sequence. Only the device which slave
address matches the incoming device address sent by the
master executes the instruction. The A1 A0 inputs can be
actively driven by CMOS input signals or tied to VCC or
VSS. The remaining two bits in the device address byte must
be set to 0.
Instruction Byte
The next byte sent to the CAT5261 contains the
instruction and register pointer information. The four most
significant bits used provide the instruction opcode I3 I0.
The R1 and R0 bits point to one of the four data registers of
each associated potentiometer. The least two significant bits
point to one of two Wiper Control Registers. The format is
shown in Figure 5.
Table 12. DATA REGISTER SELECTION
Data Register Selected
R1
R0
DR0
0
DR1
0
1
Figure 4. Identification Byte Format
ID3
ID2
ID1
ID0
A3
A2
A1
A0
01
(MSB)
(LSB)
Device Type
Identifier
Slave Address
Figure 5. Instruction Byte Format
I3
I2
I1
I0
R1
R0
P1
P0
(MSB)
(LSB)
Instruction
Data Register
WCR/Pot Selection
Opcode
Selection
WIPER CONTROL AND DATA REGISTERS
Wiper Control Register (WCR)
The CAT5261 contains two 8-bit Wiper Control
Registers, one for each potentiometer. The Wiper Control
Register output is decoded to select one of 256 switches
along its resistor array. The contents of the WCR can be
altered in four ways: it may be written by the host via Write
Wiper Control Register instruction; it may be written by
transferring the contents of one of four associated Data
Registers via the XFR Data Register instruction; it can be
modified one step at a time by the Increment/decrement
instruction (see Instruction section for more details).
Finally, it is loaded with the content of its data register zero
(DR0) upon power-up.
The Wiper Control Register is a volatile register that loses
its contents when the CAT5261 is powered-down. Although
the register is automatically loaded with the value in DR0
upon power-up, this may be different from the value present
at power-down.
Data Registers (DR)
Each potentiometer has four 8-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the associated Wiper Control Register. Any
data changes in one of the Data Registers is a non-volatile
operation and will take a maximum of 5 ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be used
as standard memory locations for system parameters or user
preference data.
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS input goes HIGH after a
write sequence is received. The status of the internal write
cycle can be monitored by issuing a Read Status command
to read the Write in Process (WIP) bit.
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