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參數(shù)資料
| 型號： | CAT5273ZI-50-GT3 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 12/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DPP 50K 256TAP 10MSOP |
| 標準包裝： | 3,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 100 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
CAT5271, CAT5273
http://onsemi.com
8
Table 9. CODES AND CORRESPONDING RWA
RESISTANCE FOR RAB = 100 kW, VDD = 5 V
D (Dec.)
RWA (W)
Output State
255
441
Full Scale
128
50,050
Midscale
1
99,659
1 LSB
0
100,050
Zero Scale
Typical device to device resistance matching is lot
dependent and may vary by up to 20%.
ESD Protection
GND
LOGIC
Digital
Input
GND
Potentiometer
Figure 15. ESD Protection Networks
W, A, B
Terminal Voltage Operating Range
The CAT5271/CAT5273 VDD and GND power supply
define the limits for proper 3-terminal digital potentiometer
operation. Signals or potentials applied to terminals A, B or
the wiper must remain inside the span of VDD and GND.
Signals which attempt to go outside these boundaries will be
clamped by the internal forward biased diodes.
W, A, B
CAT5271
LOGIC
GND
Figure 16.
VDD
Power-up Sequence
Because ESD protection diodes limit the voltage
compliance at terminals A, B, and W (see Figure 15), it is
recommended that VDD/GND be powered before applying
any voltage to terminals A, B, and W. The ideal power-up
sequence is: GND, VDD, digital inputs, and then VA/B/W. The
order of powering VA, VB, VW, and the digital inputs is not
important as long as they are powered after VDD/GND.
Power Supply Bypassing
Good design practice employs compact, minimum lead
length layout design. Leads should be as direct as possible.
It is also recommended to bypass the power supplies with
quality low ESR Ceramic chip capacitors of 0.01
mF to
0.1
mF. Low ESR 1 mF to 10 mF tantalum or electrolytic
capacitors can also be applied at the supplies to suppress
transient disturbances and low frequency ripple. As a further
precaution digital ground should be joined remotely to the
analog ground at one point to minimize the ground bounce.
CAT5271
GND
+
10 mF
0.1 mF
Figure 17. Power Supply Bypassing
VDD
C3
C1
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