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參數(shù)資料
| 型號： | CAT5273ZI-50-GT3 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 8/13頁 |
| 文件大小： | 0K |
| 描述： | IC POT DPP 50K 256TAP 10MSOP |
| 標準包裝： | 3,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 100 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
CAT5271, CAT5273
http://onsemi.com
4
Table 4. CAPACITANCE
TA = 25C, f = 1.0 MHz, VDD = 5 V
Symbol
Test
Conditions
Max
Units
CI/O
(Note 11)
Input/Output Capacitance (SDA, SCL)
VI/O = 0 V
8
pF
Symbol
Parameter
Max
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
11. This parameter is tested initially and after a design or process change that affects the parameter.
12.tPUR and t PUW are delays required from the time VCC is stable until the specified operation can be initiated.
Table 6. DIGITAL POTENTIOMETER TIMING
Symbol
Parameter
Min
Max
Units
tWRPO
Wiper Response Time After Power Supply Stable
50
ms
tWR
Wiper Response Time: SCL falling edge after last bit of wiper position data byte to
wiper change
20
ms
Table 7. A.C. CHARACTERISTICS
VDD = +2.7 V to +5.5 V, 40C to +85C unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Units
fSCL
Clock Frequency
400
kHz
tHIGH
Clock High Period
600
ns
tLOW
Clock Low Period
1300
ns
tSU:STA
Start Condition Setup Time (for a Repeated Start Condition)
600
ns
tHD:STA
Start Condition Hold Time
600
ns
tSU:DAT
Data in Setup Time
100
ns
tHD:DAT
Data in Hold Time
0
ns
tSU:STO
Stop Condition Setup Time
600
ns
tBUF
Time the bus must be free before a new transmission can start
1300
ns
tR
SDA and SCL Rise Time
300
ns
tF
SDA and SCL Fall Time
300
ns
tDH
Data Out Hold Time
100
ns
TI
Noise Suppression Time Constant at SCL, SDA Inputs
50
ns
tAA
SCL Low to SDA Data Out and ACK Out
1
ms
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