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參數資料
| 型號： | CBTL06DP212EE |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 編、解碼器及復用、解復用 |
| 英文描述： | High-performance DisplayPort Gen2 2 : 1 multiplexer |
| 中文描述： | MULTIPLEXER, PBGA48 |
| 封裝： | 5 X 5 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, TFBGA-48 |
| 文件頁數： | 14/18頁 |
| 文件大小： | 147K |
| 代理商： | CBTL06DP212EE |
CBTL06DP212
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
5 of 18
NXP Semiconductors
CBTL06DP212
High-performance DisplayPort Gen2 2 : 1 multiplexer
7.2 Pin description
Table 3.
Pin description
Symbol
Ball
Type
Description
GPU_SEL
A1
3.3 V CMOS
single-ended input
Selects between two multiplexer/switch paths. When HIGH, path 2
left-side is connected to its corresponding right-side I/O. When
LOW, path 1 left-side is connected to its corresponding right-side
I/O.
DDC_AUX_SEL
C2
3.3 V CMOS
single-ended input
Selects between DDC and AUX paths. When HIGH, the CLK and
DAT I/Os are connected to their respective DDCOUT terminals.
When LOW, the AUX+ and AUX
I/Os are connected to their
respective DDCOUT terminals.
TST0
B7
3.3 V CMOS
single-ended input
Test pin for NXP use only. Should be tied to VDD in normal
operation.
IN1_0+
B4
differential I/O
Four high-speed differential pairs for DisplayPort or PCI Express
signals, path 1, left-side.
IN1_0
A4
differential I/O
IN1_1+
B5
differential I/O
IN1_1
A5
differential I/O
IN1_2+
B6
differential I/O
IN1_2
A6
differential I/O
IN1_3+
A8
differential I/O
IN1_3
A9
differential I/O
IN2_0+
B8
differential I/O
Four high-speed differential pairs for DisplayPort or PCI Express
signals, path 2, left-side.
IN2_0
B9
differential I/O
IN2_1+
D8
differential I/O
IN2_1
D9
differential I/O
IN2_2+
E8
differential I/O
IN2_2
E9
differential I/O
IN2_3+
F8
differential I/O
IN2_3
F9
differential I/O
OUT_0+
B2
differential I/O
Four high-speed differential pairs for DisplayPort or PCI Express
signals, right-side.
OUT_0
B1
differential I/O
OUT_1+
D2
differential I/O
OUT_1
D1
differential I/O
OUT_2+
E2
differential I/O
OUT_2
E1
differential I/O
OUT_3+
F2
differential I/O
OUT_3
F1
differential I/O
AUX1+
H9
differential I/O
High-speed differential pair for AUX signals, path 1, left-side.
AUX1
J9
differential I/O
AUX2+
H6
differential I/O
High-speed differential pair for AUX signals, path 2, left-side.
AUX2
J6
differential I/O
DDC_CLK1
H8
differential I/O
Pair of single-ended terminals for DDC clock and data signals,
path 1, left-side.
DDC_DAT1
J8
differential I/O
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CBTL06DP212EE,118 | 功能描述:編碼器、解碼器、復用器和解復用器 GEN 2 5.4 GBPS 6CH 2:1 MULTIPLEXER RoHS:否 制造商:Micrel 產品:Multiplexers 邏輯系列:CMOS 位數: 線路數量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| CBTL06DP213EE,118 | 功能描述:編碼器、解碼器、復用器和解復用器 DISPLAYPORT MULTIPLEXER RoHS:否 制造商:Micrel 產品:Multiplexers 邏輯系列:CMOS 位數: 線路數量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| CBTL06GP212 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:High performance DisplayPort switch with high common-mode voltage support |
| CBTL06GP212EE,118 | 制造商:NXP Semiconductors 功能描述:CBTL06GP212EE/TFBGA48/REEL13// - Tape and Reel 制造商:NXP Semiconductors 功能描述:IC MUX 6CH DISPLAY PORT 48TFBGA |
| CBTL06GP212EE-G | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:High performance DisplayPort switch with high common-mode voltage support |
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